420 lines
9.1 KiB
C
420 lines
9.1 KiB
C
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/* isp/piris.c
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*
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* Copyright (c) 2006 Hisilicon Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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* History:
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* 23-march-2011 create this file
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/miscdevice.h>
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#include <linux/fcntl.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/workqueue.h>
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#include <linux/hrtimer.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include "piris.h"
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#include "piris_ext.h"
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#define PIRISI_ADRESS_BASE 0x20210000 // Piris use GPIO13
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void __iomem* reg_pirisI_base_va = 0;
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#define HI_IO_PIRISI_ADDRESS(x) (reg_pirisI_base_va + ((x)-(PIRISI_ADRESS_BASE)))
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#define PIRIS_CFG_REG HI_IO_PIRISI_ADDRESS(PIRISI_ADRESS_BASE + 0x007C)
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#define PIRIS_CTRL_REG HI_IO_PIRISI_ADDRESS(PIRISI_ADRESS_BASE + 0x0400)
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#define PIRIS_WRITE_REG(Addr, Value) ((*(volatile unsigned int *)(Addr)) = (Value))
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#define PIRIS_READ_REG(Addr) (*(volatile unsigned int *)(Addr))
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#define MAX(a, b) (a > b? a : b)
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#define MIN(a, b) (a < b? a : b)
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#define MAX_MOTOR_PAHSE 4
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#define MAX_STEPS 92
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#define PIRIS_PPS 100
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static const unsigned char motor_phase_tbl[MAX_MOTOR_PAHSE] = { 0x0, 0x1, 0x2, 0x3};
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typedef struct hiPIRIS_DEV
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{
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int src_pos;
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int dest_pos;
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unsigned int pps;
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int phase;
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const unsigned char* phase_tbl;
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struct semaphore sem;
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struct timer_list timer;
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} PIRIS_DEV;
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static PIRIS_DEV* p_piris_dev;
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DECLARE_COMPLETION(piris_comp);
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int piris_gpio_update(int* pPirisPos)
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{
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p_piris_dev->dest_pos = *pPirisPos;
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p_piris_dev->pps = PIRIS_PPS;
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p_piris_dev->pps = MAX(MIN(p_piris_dev->pps, HZ), 1);
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p_piris_dev->timer.expires = jiffies + HZ / p_piris_dev->pps;
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/* whether piris timer already at the kerbel timer pending list */
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if (p_piris_dev->timer.entry.next != NULL)
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{
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return -1;
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}
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add_timer(&p_piris_dev->timer);
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return 0;
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}
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/* first go to the full open iris step, set the full open as origin */
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int piris_origin_set(PIRIS_DATA_S* pstPirisData)
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{
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int piris_pos;
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piris_pos = pstPirisData->CurPos;
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piris_gpio_update(&piris_pos);
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// wait for piris origin done
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init_completion(&piris_comp);
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wait_for_completion(&piris_comp);
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if (pstPirisData->ZeroIsMax == 1)
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{
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p_piris_dev->src_pos = 0;
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p_piris_dev->dest_pos = 0;
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}
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else
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{
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p_piris_dev->src_pos = pstPirisData->TotalStep - 1;
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p_piris_dev->dest_pos = pstPirisData->TotalStep - 1;
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}
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return 0;
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}
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/* go to the full close iris step */
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int piris_close_set(PIRIS_DATA_S* pstPirisData)
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{
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int piris_pos;
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piris_pos = pstPirisData->CurPos;
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piris_gpio_update(&piris_pos);
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// wait for piris origin done
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init_completion(&piris_comp);
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wait_for_completion(&piris_comp);
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if (pstPirisData->ZeroIsMax == 1)
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{
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p_piris_dev->src_pos = pstPirisData->TotalStep - 1;
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p_piris_dev->dest_pos = pstPirisData->TotalStep - 1;
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}
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else
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{
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p_piris_dev->src_pos = 0;
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p_piris_dev->dest_pos = 0;
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}
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return 0;
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}
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/* file operation */
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int piris_open(struct inode* inode, struct file* file)
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{
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file->private_data = p_piris_dev;
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return 0 ;
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}
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int piris_close(struct inode* inode, struct file* file)
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{
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return 0;
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}
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#if 0
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static int PIRIS_DRV_Disable(void)
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{
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PIRIS_WRITE_REG(PIRIS_CTRL_REG, 0x1F);
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PIRIS_WRITE_REG(PIRIS_CFG_REG, 0x10);
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return 0;
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}
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#endif
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int PIRIS_DRV_Write(unsigned char bits)
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{
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switch (bits)
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{
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case 0:
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PIRIS_WRITE_REG(PIRIS_CTRL_REG, 0x1F);
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PIRIS_WRITE_REG(PIRIS_CFG_REG , 0x15);
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break;
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case 1:
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PIRIS_WRITE_REG(PIRIS_CTRL_REG, 0x1F);
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PIRIS_WRITE_REG(PIRIS_CFG_REG , 0x16);
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break;
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case 2:
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PIRIS_WRITE_REG(PIRIS_CTRL_REG, 0x1F);
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PIRIS_WRITE_REG(PIRIS_CFG_REG , 0x1A);
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break;
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case 3:
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PIRIS_WRITE_REG(PIRIS_CTRL_REG, 0x1F);
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PIRIS_WRITE_REG(PIRIS_CFG_REG , 0x19);
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break;
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default:
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break;
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}
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return 0;
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}
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static long piris_ioctl(struct file* file, unsigned int cmd, unsigned long arg)
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{
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int __user* pPirisPos;
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PIRIS_DATA_S __user* argp;
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PIRIS_STATUS_E __user* pPirisStatus;
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PIRIS_DEV* pstPirisDev = (PIRIS_DEV*) file->private_data;
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int err = 0;
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if (_IOC_TYPE(cmd) != PIRIS_IOC_MAGIC)
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{
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return -ENOTTY;
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}
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if (_IOC_NR(cmd) > PIRIS_IOC_MAXNR)
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{
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return -ENOTTY;
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}
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if (_IOC_DIR(cmd) & _IOC_READ)
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{
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err = !access_ok(VERIFY_WRITE, (void __user*)arg, _IOC_SIZE(cmd));
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}
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else if (_IOC_DIR(cmd) & _IOC_WRITE)
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{
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err = !access_ok(VERIFY_READ, (void __user*)arg, _IOC_SIZE(cmd));
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}
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if (err)
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{
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return -EFAULT;
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}
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// lock pstPirisDev
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if (down_interruptible(&pstPirisDev->sem))
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{
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return -ERESTARTSYS;
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}
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switch (cmd)
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{
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case PIRIS_SET_ACT_ARGS:
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pPirisPos = (int __user*)arg;
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piris_gpio_update(pPirisPos);
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break;
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case PIRIS_SET_ORGIN:
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argp = (PIRIS_DATA_S __user*)arg;
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piris_origin_set(argp);
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break;
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case PIRIS_SET_CLOSE:
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argp = (PIRIS_DATA_S __user*)arg;
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piris_close_set(argp);
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break;
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case PIRIS_GET_STATUS:
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pPirisStatus = (PIRIS_STATUS_E __user*)arg;
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if (pstPirisDev->dest_pos != pstPirisDev->src_pos)
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{
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*pPirisStatus = PIRIS_BUSY;
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}
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else
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{
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*pPirisStatus = PIRIS_IDLE;
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//PIRIS_DRV_Disable();
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}
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break;
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default: /* redundant, as cmd was checked against MAXNR */
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break;
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}
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// unlock pstPirisDev
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up(&pstPirisDev->sem);
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return 0 ;
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}
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static struct file_operations piris_fops =
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{
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.owner = THIS_MODULE,
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.unlocked_ioctl = piris_ioctl ,
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.open = piris_open ,
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.release = piris_close ,
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};
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static struct miscdevice gstPirisDev =
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{
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.minor = MISC_DYNAMIC_MINOR,
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.name = "piris" ,
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.fops = &piris_fops,
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};
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void piris_timer_cb(unsigned long arg)
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{
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int sign = 1;
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unsigned char bits;
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PIRIS_DEV* pstPirisDev = (PIRIS_DEV*)arg;
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if (pstPirisDev->src_pos == pstPirisDev->dest_pos)
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{
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return ;
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}
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sign = (pstPirisDev->dest_pos - pstPirisDev->src_pos < 0) ? -1 : 1;
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pstPirisDev->src_pos += sign;
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// close iris: 0->1->2->3->0; open iris: 3->2->1->0->3
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pstPirisDev->phase = (pstPirisDev->phase + MAX_MOTOR_PAHSE + sign) % MAX_MOTOR_PAHSE;
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bits = pstPirisDev->phase_tbl[pstPirisDev->phase];
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PIRIS_DRV_Write(bits);
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if (pstPirisDev->dest_pos == pstPirisDev->src_pos)
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{
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complete(&piris_comp);
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}
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pstPirisDev->timer.expires = jiffies + HZ / pstPirisDev->pps;
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add_timer(&pstPirisDev->timer);
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//printk("%s, pos :%d @ pps:%d\n", __FUNCTION__, pstPirisDev->src_pos, pstPirisDev->pps);
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return ;
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}
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static int hi_piris_isp_register(void)
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{
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ISP_PIRIS_CALLBACK_S stPirisCb = {0};
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stPirisCb.pfn_piris_gpio_update = (HI_S32 (*)(HI_S32))piris_gpio_update;
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if (CKFN_ISP_RegisterPirisCallBack())
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{
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CALL_ISP_RegisterPirisCallBack(0, &stPirisCb);
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}
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else
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{
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printk("register piris_gpio_write_callback to isp failed, hi_piris init is failed!\n");
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return -1;
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}
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return 0;
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}
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/* module init and exit */
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static int __init piris_init(void)
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{
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int ret;
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p_piris_dev = kmalloc(sizeof(PIRIS_DEV), GFP_KERNEL);
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if (!p_piris_dev)
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{
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return -1;
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}
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memset(p_piris_dev, 0x0, sizeof(PIRIS_DEV));
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sema_init(&p_piris_dev->sem, 1);
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init_completion(&piris_comp);
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// init timer
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init_timer(&p_piris_dev->timer);
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p_piris_dev->timer.function = piris_timer_cb;
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p_piris_dev->timer.data = (unsigned long)p_piris_dev;
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p_piris_dev->timer.expires = jiffies + HZ; /* one second */
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p_piris_dev->phase_tbl = motor_phase_tbl;
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reg_pirisI_base_va = ioremap_nocache(PIRISI_ADRESS_BASE, 0x10000);
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ret = misc_register(&gstPirisDev);
|
||
|
|
|
||
|
|
hi_piris_isp_register();
|
||
|
|
|
||
|
|
if (ret != 0)
|
||
|
|
{
|
||
|
|
printk("register piris device failed with %#x!\n", ret);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit piris_exit(void)
|
||
|
|
{
|
||
|
|
del_timer(&p_piris_dev->timer);
|
||
|
|
kfree(p_piris_dev);
|
||
|
|
|
||
|
|
misc_deregister(&gstPirisDev);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
module_init(piris_init);
|
||
|
|
module_exit(piris_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("piris driver");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_AUTHOR("hisilicon");
|
||
|
|
|