445 lines
9.2 KiB
C
445 lines
9.2 KiB
C
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/* extdrv/interface/ssp/hi_ssp.c
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*
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* Copyright (c) 2006 Hisilicon Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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* History:
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* 21-April-2006 create this file
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*/
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/fcntl.h>
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#include <linux/mm.h>
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#include <linux/proc_fs.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <linux/miscdevice.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/poll.h>
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#include <asm/bitops.h>
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#include <asm/uaccess.h>
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#include <asm/irq.h>
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#include <linux/moduleparam.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include "hi_ssp.h"
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#define ssp_readw(addr,ret) (ret =(*(volatile unsigned int *)(addr)))
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#define ssp_writew(addr,value) ((*(volatile unsigned int *)(addr)) = (value))
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#define HI_REG_READ(addr,ret) (ret =(*(volatile unsigned int *)(addr)))
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#define HI_REG_WRITE(addr,value) ((*(volatile unsigned int *)(addr)) = (value))
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#define SSP_BASE 0x200E0000
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#define SSP_SIZE 0x10000 // 64KB
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#define SSP_INT 65 // Interrupt No.
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void __iomem* reg_ssp_base_va;
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#define IO_ADDRESS_VERIFY(x) (reg_ssp_base_va + ((x)-(SSP_BASE)))
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/* SSP register definition .*/
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#define SSP_CR0 IO_ADDRESS_VERIFY(SSP_BASE + 0x00)
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#define SSP_CR1 IO_ADDRESS_VERIFY(SSP_BASE + 0x04)
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#define SSP_DR IO_ADDRESS_VERIFY(SSP_BASE + 0x08)
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#define SSP_SR IO_ADDRESS_VERIFY(SSP_BASE + 0x0C)
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#define SSP_CPSR IO_ADDRESS_VERIFY(SSP_BASE + 0x10)
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#define SSP_IMSC IO_ADDRESS_VERIFY(SSP_BASE + 0x14)
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#define SSP_RIS IO_ADDRESS_VERIFY(SSP_BASE + 0x18)
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#define SSP_MIS IO_ADDRESS_VERIFY(SSP_BASE + 0x1C)
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#define SSP_ICR IO_ADDRESS_VERIFY(SSP_BASE + 0x20)
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#define SSP_DMACR IO_ADDRESS_VERIFY(SSP_BASE + 0x24)
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void hi_ssp_writeOnly(int bWriteOnly)
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{
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int ret = 0;
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bWriteOnly = 0;
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ssp_readw(SSP_CR1, ret);
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if (bWriteOnly)
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{
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ret = ret | (0x1 << 5);
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}
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else
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{
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ret = ret & (~(0x1 << 5));
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}
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ssp_writew(SSP_CR1, ret);
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}
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void hi_ssp_enable(void)
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{
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int ret = 0;
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ssp_readw(SSP_CR1, ret);
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ret = (ret & 0xFFFD) | 0x2;
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ret = ret | (0x1 << 4); /* big/little end, 1: little, 0: big */
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ret = ret | (0x1 << 15); /* wait en */
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ssp_writew(SSP_CR1, ret);
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hi_ssp_writeOnly(0);
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}
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void hi_ssp_disable(void)
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{
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int ret = 0;
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ssp_readw(SSP_CR1, ret);
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ret = ret & (~(0x1 << 1));
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ssp_writew(SSP_CR1, ret);
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}
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int hi_ssp_set_frameform(unsigned char framemode, unsigned char spo, unsigned char sph, unsigned char datawidth)
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{
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int ret = 0;
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ssp_readw(SSP_CR0, ret);
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if (framemode > 3)
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{
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printk("set frame parameter err.\n");
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return -1;
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}
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ret = (ret & 0xFFCF) | (framemode << 4);
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if ((ret & 0x30) == 0)
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{
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if (spo > 1)
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{
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printk("set spo parameter err.\n");
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return -1;
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}
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if (sph > 1)
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{
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printk("set sph parameter err.\n");
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return -1;
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}
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ret = (ret & 0xFF3F) | (sph << 7) | (spo << 6);
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}
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if ((datawidth > 16) || (datawidth < 4))
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{
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printk("set datawidth parameter err.\n");
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return -1;
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}
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ret = (ret & 0xFFF0) | (datawidth - 1);
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ssp_writew(SSP_CR0, ret);
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return 0;
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}
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int hi_ssp_set_serialclock(unsigned char scr, unsigned char cpsdvsr)
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{
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int ret = 0;
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ssp_readw(SSP_CR0, ret);
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ret = (ret & 0xFF) | (scr << 8);
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ssp_writew(SSP_CR0, ret);
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if ((cpsdvsr & 0x1))
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{
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printk("set cpsdvsr parameter err.\n");
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return -1;
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}
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ssp_writew(SSP_CPSR, cpsdvsr);
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return 0;
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}
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int hi_ssp_alt_mode_set(int enable)
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{
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int ret = 0;
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ssp_readw(SSP_CR1, ret);
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if (enable)
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{
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ret = ret & (~0x40);
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}
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else
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{
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ret = (ret & 0xFF) | 0x40;
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}
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ssp_writew(SSP_CR1, ret);
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return 0;
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}
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void hi_ssp_writedata(unsigned short sdata)
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{
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ssp_writew(SSP_DR, sdata);
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udelay(2);
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}
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int hi_ssp_readdata(void)
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{
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int ret = 0;
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ssp_readw(SSP_DR, ret);
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return ret;
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}
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static void spi_enable(void)
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{
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HI_REG_WRITE(SSP_CR1, 0x42);
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}
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static void spi_disable(void)
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{
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HI_REG_WRITE(SSP_CR1, 0x40);
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}
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int hi_ssp_lcd_init_cfg(void)
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{
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unsigned char framemode = 0;
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unsigned char spo = 1;
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unsigned char sph = 1;
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unsigned char datawidth = 9;
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#ifdef HI_FPGA
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unsigned char scr = 1;
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unsigned char cpsdvsr = 2;
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#else
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unsigned char scr = 8;
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unsigned char cpsdvsr = 8;
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#endif
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spi_disable();
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hi_ssp_set_frameform(framemode, spo, sph, datawidth);
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hi_ssp_set_serialclock(scr, cpsdvsr);
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hi_ssp_alt_mode_set(1);
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hi_ssp_enable();
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return 0;
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}
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void spi_write_a9byte(unsigned char cmd_dat, unsigned char dat)
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{
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unsigned short spi_data = 0;
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if (cmd_dat)
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{
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spi_data = 1 << 8;
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}
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else
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{
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spi_data = 0 << 8;
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}
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spi_data = spi_data | dat;
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spi_enable();
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//hi_ssp_writedata(spi_data);
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ssp_writew(SSP_DR, spi_data);
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printk("spi_data:0x%x\n", spi_data);
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msleep(10);
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spi_disable();
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}
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void spi_write_a16byte(unsigned short spi_dat)
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{
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spi_enable();
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//hi_ssp_writedata(spi_data);
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ssp_writew(SSP_DR, spi_dat);
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printk("spi_data:0x%x\n", spi_dat);
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msleep(10);
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spi_disable();
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}
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void ssp_write_dat(unsigned char dat)
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{
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spi_write_a9byte(1, dat);
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}
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void ssp_write_cmd(unsigned char dat)
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{
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spi_write_a9byte(0, dat);
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}
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long ssp_lcd_ioctl(struct file* file, unsigned int cmd, unsigned long arg)
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{
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unsigned char val;
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unsigned short val_16;
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switch (cmd)
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{
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case SSP_LCD_READ_ALT:
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break;
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case SSP_LCD_WRITE_CMD:
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val = *(unsigned int*)arg;
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spi_write_a9byte(0, val);
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//printk("SSP_LCD_WRITE_CMD!\n");
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break;
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case SSP_LCD_WRITE_DAT:
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val = *(unsigned int*)arg;
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spi_write_a9byte(1, val);
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break;
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case SSP_LCD_WRITE_CMD16:
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val_16 = *(unsigned int*)arg;
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spi_write_a16byte(val_16);
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break;
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default:
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{
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printk("Kernel: No such ssp command %#x!\n", cmd);
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return -1;
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}
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}
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return 0;
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}
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int ssp_lcd_open(struct inode* inode, struct file* file)
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{
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return 0;
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}
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int ssp_lcd_close(struct inode* inode, struct file* file)
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{
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return 0;
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}
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static struct file_operations ssp_lcd_fops =
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{
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.owner = THIS_MODULE,
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.unlocked_ioctl = ssp_lcd_ioctl,
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.open = ssp_lcd_open,
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.release = ssp_lcd_close
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};
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static struct miscdevice ssp_lcd_dev =
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{
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.minor = MISC_DYNAMIC_MINOR,
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.name = "ssp_lcd",
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.fops = &ssp_lcd_fops,
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};
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void lcd_ota5182_init(void)
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{
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/*spi_16bit_setting*/
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unsigned char framemode = 0;
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unsigned char spo = 1;
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unsigned char sph = 1;
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unsigned char datawidth = 16;
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#ifdef HI_FPGA
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unsigned char scr = 1;
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unsigned char cpsdvsr = 2;
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#else
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unsigned char scr = 8;
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unsigned char cpsdvsr = 8;
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#endif
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spi_disable();
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hi_ssp_set_frameform(framemode, spo, sph, datawidth);
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hi_ssp_set_serialclock(scr, cpsdvsr);
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hi_ssp_alt_mode_set(1);
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hi_ssp_enable();
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/*LCD ILI9341 VERTICAL SETTING*/
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//ssp_write_cmd(0x01);//software reset
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spi_write_a16byte(0x000f);
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|||
|
|
spi_write_a16byte(0x0005);
|
|||
|
|
msleep(10);
|
|||
|
|
spi_write_a16byte(0x000f);
|
|||
|
|
spi_write_a16byte(0x0005);
|
|||
|
|
msleep(10);
|
|||
|
|
spi_write_a16byte(0x000f);
|
|||
|
|
spi_write_a16byte(0x5000);
|
|||
|
|
msleep(10);
|
|||
|
|
//spi_write_a16byte(0x10E4);
|
|||
|
|
spi_write_a16byte(0x1004);//ʱ<><CAB1>
|
|||
|
|
spi_write_a16byte(0x3008);
|
|||
|
|
spi_write_a16byte(0x7040);//brightness
|
|||
|
|
spi_write_a16byte(0xA000);
|
|||
|
|
spi_write_a16byte(0xC003);
|
|||
|
|
spi_write_a16byte(0xE013);
|
|||
|
|
spi_write_a16byte(0x6001);//<2F><><EFBFBD>У<EFBFBD>Ƶ<EFBFBD><C6B5>ѡ<EFBFBD><D1A1>
|
|||
|
|
msleep(100);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
static int __init hi_ssp_lcd_init(void)
|
|||
|
|
{
|
|||
|
|
int ret;
|
|||
|
|
|
|||
|
|
reg_ssp_base_va = ioremap_nocache((unsigned long)SSP_BASE, (unsigned long)SSP_SIZE);
|
|||
|
|
if (!reg_ssp_base_va)
|
|||
|
|
{
|
|||
|
|
printk("Kernel: ioremap ssp base failed!\n");
|
|||
|
|
return -ENOMEM;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
ret = misc_register(&ssp_lcd_dev);
|
|||
|
|
if (0 != ret)
|
|||
|
|
{
|
|||
|
|
printk("Kernel: register ssp_0 device failed!\n");
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
printk("lcd is 0ta5182\n");
|
|||
|
|
lcd_ota5182_init();
|
|||
|
|
printk("Kernel: ssp_lcd initial ok!\n");
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
static void __exit hi_ssp_lcd_exit(void)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
hi_ssp_disable();
|
|||
|
|
|
|||
|
|
iounmap((void*)reg_ssp_base_va);
|
|||
|
|
|
|||
|
|
misc_deregister(&ssp_lcd_dev);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
module_init(hi_ssp_lcd_init);
|
|||
|
|
module_exit(hi_ssp_lcd_exit);
|
|||
|
|
|
|||
|
|
MODULE_LICENSE("GPL");
|
|||
|
|
|