304 lines
8.5 KiB
C
304 lines
8.5 KiB
C
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/******************************************************************************
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Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd.
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******************************************************************************
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File Name : hi_defines.h
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Version : Initial Draft
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Author : Hisilicon multimedia software group
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Created : 2005/4/23
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Last Modified :
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Description : The common data type defination
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Function List :
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History :
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******************************************************************************/
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#ifndef __HI_DEFINES_H__
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#define __HI_DEFINES_H__
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#ifdef __cplusplus
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#if __cplusplus
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extern "C"{
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#endif
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#endif /* __cplusplus */
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#define HI3516A_V100 0x3516A100
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#define HI3516D_V100 0x3516D100
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#define HI3518E_V200 0x3518E200
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#define HI35xx_Vxxx 0x35000000
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#ifndef HICHIP
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#define HICHIP HI3518E_V200
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#endif
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#if HICHIP==HI3516A_V100
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#define CHIP_NAME "Hi3516A"
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#define MPP_VER_PRIX "_MPP_V"
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#elif HICHIP==HI3518E_V200
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#define CHIP_NAME "Hi3518EV200"
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#define MPP_VER_PRIX "_MPP_V"
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#elif HICHIP==HI35xx_Vxxx
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#error HuHu, I am an dummy chip
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#else
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#error HICHIP define may be error
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#endif
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#define LINE_LEN_BIT 5
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#define LINE_LEN (1<<LINE_LEN_BIT)
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#define LINE_BASE_MASK (~(LINE_LEN-1))
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static inline void InvalidateDcache(unsigned long addr, unsigned long len)
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{
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unsigned long end;
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//TODO: cacheˢ<65><CBA2><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>д
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return ;
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addr &= LINE_BASE_MASK;
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len >>= LINE_LEN_BIT;
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end = addr + len*LINE_LEN;
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while(addr != end)
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{
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asm("mcr p15, 0, %0, c7, c6, 1"::"r"(addr));
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addr += LINE_LEN;
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}
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return;
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}
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static inline void FlushDcache(unsigned long addr, unsigned long len)
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{
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unsigned long end;
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//TODO: cacheˢ<65><CBA2><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>д
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return ;
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addr &= LINE_BASE_MASK;
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len >>= LINE_LEN_BIT;
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end = addr + len*LINE_LEN;
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while(addr != end)
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{
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asm("mcr p15, 0, %0, c7, c10, 1"::"r"(addr));
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addr += LINE_LEN;
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}
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return;
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}
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#define DEFAULT_ALIGN 16
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#define MAX_MMZ_NAME_LEN 16
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#define MAX_NODE_NUM 16
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/* For VDA */
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#define VDA_MAX_NODE_NUM 32
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#define VDA_MAX_INTERNAL 256
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#define VDA_CHN_NUM_MAX 32
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#define VDA_MAX_WIDTH 960
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#define VDA_MAX_HEIGHT 960
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#define VDA_MIN_WIDTH 32
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#define VDA_MIN_HEIGHT 32
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/* For VENC */
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#define VENC_MAX_NAME_LEN 16
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#define VENC_MAX_CHN_NUM 16
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#define VENC_MAX_GRP_NUM 16
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#define H264E_MAX_WIDTH 1920
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#define H264E_MAX_HEIGHT 1920
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#define H264E_MIN_WIDTH 160
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#define H264E_MIN_HEIGHT 64
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#define H265E_MAX_WIDTH 2592
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#define H265E_MAX_HEIGHT 2592
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#define H265E_MIN_WIDTH 128
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#define H265E_MIN_HEIGHT 128
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#define JPEGE_MAX_WIDTH 8192
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#define JPEGE_MAX_HEIGHT 8192
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#define JPEGE_MIN_WIDTH 64
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#define JPEGE_MIN_HEIGHT 64
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#define VENC_MAX_ROI_NUM 8 /* <20><><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>8<EFBFBD><38>ROI<4F><49><EFBFBD><EFBFBD> */
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#define H264E_MIN_HW_INDEX 0
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#define H264E_MAX_HW_INDEX 11
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#define H264E_MIN_VW_INDEX 0
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#define H264E_MAX_VW_INDEX 3
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/* For RC */
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#define RC_TEXTURE_THR_SIZE 12
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#define RC_RQRATIO_SIZE 8
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/* For VDEC, hi3516a not support */
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#define VDEC_MAX_CHN_NUM 0
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/* For Region */
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/* For Region */
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#define RGN_MIN_WIDTH 2
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#define RGN_MIN_HEIGHT 2
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#define RGN_MAX_WIDTH 2592
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#define RGN_MAX_HEIGHT 2592
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#define RGN_ALIGN 2
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#define RGN_HANDLE_MAX 1024
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#define COVER_MAX_NUM_VI 0
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#define COVEREX_MAX_NUM_VI 16
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#define OVERLAY_MAX_NUM_VI 0
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#define OVERLAYEX_MAX_NUM_VI 16
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#define OVERLAY_MAX_NUM_VENC 8
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#define COVER_MAX_NUM_VPSS 8
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#define COVEREX_MAX_NUM_VPSS 8
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#define OVERLAY_MAX_NUM_VPSS 1
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#define OVERLAYEX_MAX_NUM_VPSS 8
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#define OVERLAYEX_MAX_NUM_VGS 1
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#define COVER_MAX_NUM_VGS 1
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#define COVEREX_MAX_NUM_VO 1
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#define OVERLAYEX_MAX_NUM_VO 1
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#define OVERLAYEX_MAX_NUM_PCIV 0
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/* number of channle and device on video input unit of chip
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* Note! VIU_MAX_CHN_NUM is NOT equal to VIU_MAX_DEV_NUM
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* multiplied by VIU_MAX_CHN_NUM, because all VI devices
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* can't work at mode of 4 channles at the same time.
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*/
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#define VIU_MAX_DEV_NUM 1
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#define VIU_MAX_WAY_NUM_PER_DEV 1
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#define VIU_MAX_CHN_NUM_PER_DEV 1
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#define VIU_MAX_PHYCHN_NUM 1
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#define VIU_MAX_RAWCHN_NUM 1 /* raw data chn, DVR/NVR: 0 */
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#define VIU_EXT_CHN_START VIU_MAX_PHYCHN_NUM
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#define VIU_MAX_EXT_CHN_NUM 16
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#define VIU_MAX_EXTCHN_BIND_PER_CHN 8
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#define VIU_MAX_CHN_NUM (VIU_MAX_PHYCHN_NUM + VIU_MAX_EXT_CHN_NUM)
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#define VIU_MAX_UFLIST_NUM (VIU_MAX_CHN_NUM + VIU_MAX_RAWCHN_NUM)
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#define VIU_CHNID_DEV_FACTOR 2
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/* 3516a<36><61><EFBFBD><EFBFBD>֧<EFBFBD>ּ<EFBFBD><D6BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8><EFBFBD><EFBFBD>Щ<EFBFBD><D0A9>Ϣ<EFBFBD><CFA2>ֻ<EFBFBD><D6BB>Ϊ<EFBFBD>˱<EFBFBD><CBB1><EFBFBD>ͨ<EFBFBD><CDA8> */
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#define VIU_MAX_CAS_CHN_NUM 2
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#define VIU_SUB_CHN_START 16 /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>*/
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#define VIU_CAS_CHN_START 32 /* <20><><EFBFBD>弶<EFBFBD><E5BCB6>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>*/
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/* max number of VBI region*/
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#define VIU_MAX_VBI_NUM 2
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/* max length of one VBI region (by word) */
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#define VIU_MAX_VBI_LEN 8
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#define VO_MIN_CHN_WIDTH 32 /* channel minimal width */
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#define VO_MIN_CHN_HEIGHT 32 /* channel minimal height */
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#define VO_MAX_ZOOM_RATIO 1000 /* max zoom ratio, 1000 means 100% scale */
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#define VO_MAX_DEV_NUM 1 /* max dev num */
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#define VO_MAX_LAYER_NUM 1 /* max layer num */
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#define PIP_MAX_CHN_NUM 8
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#define VHD_MAX_CHN_NUM 8 /* max VHD chn num */
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#define VO_MAX_CHN_NUM VHD_MAX_CHN_NUM /* max chn num */
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#define VO_MAX_LAYER_IN_DEV 1 /* max layer num of each dev */
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#define VO_MIN_CHN_LINE 2
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#define VO_MAX_GFX_LAYER_PER_DEV 1
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#define VO_MAX_GRAPHICS_LAYER_NUM 1
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#define MDDRC_ZONE_MAX_NUM 32
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#define VO_MAX_PRIORITY 2
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#define VO_MIN_TOLERATE 1 /* min play toleration 1ms */
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#define VO_MAX_TOLERATE 100000 /* max play toleration 100s */
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#define AI_DEV_MAX_NUM 1
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#define AO_DEV_MIN_NUM 0
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#define AO_DEV_MAX_NUM 1
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#define AIO_MAX_NUM 1
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#define AIO_MAX_CHN_NUM 16
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#define AENC_MAX_CHN_NUM 32
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#define ADEC_MAX_CHN_NUM 32
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/* For VPSS */
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#define VPSS_MAX_GRP_NUM 32
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#define VPSS_MAX_PHY_CHN_NUM 4
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#define VPSS_MAX_EXT_CHN_NUM 8
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#define VPSS_MAX_CHN_NUM (VPSS_MAX_PHY_CHN_NUM + VPSS_MAX_EXT_CHN_NUM)
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/* For pciv, hi3516a not support */
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#define PCIV_MAX_CHN_NUM 0 /* max pciv channel number in each pciv device */
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/* VB size calculate for compressed frame.
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[param input]
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w: width
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h: height
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fmt: pixel format, 0: SP420, 1: SP422
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z: compress mode, 0: no compress, 1: default compress
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[param output]
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size: vb blk size
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*/
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#define VB_W_ALIGN 16
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#define VB_H_ALIGN 2
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#define VB_HEADER_STRIDE 16
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#define VB_ALIGN(x, a) ((a) * (((x) + (a) - 1) / (a)))
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#define VB_PIC_Y_HEADER_SIZE(Width, Height, size)\
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do{\
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size = VB_HEADER_STRIDE * (Height);\
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}while(0)
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#define VB_PIC_HEADER_SIZE(Width, Height, Type, size)\
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do{\
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if (PIXEL_FORMAT_YUV_SEMIPLANAR_422 == Type || PIXEL_FORMAT_RGB_BAYER == Type )\
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{\
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size = VB_HEADER_STRIDE * (Height) * 2;\
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}\
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else if(PIXEL_FORMAT_YUV_SEMIPLANAR_420 == Type)\
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{\
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size = (VB_HEADER_STRIDE * (Height) * 3) >> 1;\
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}\
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else if(PIXEL_FORMAT_SINGLE == Type)\
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{\
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size = VB_HEADER_STRIDE * (Height);\
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}\
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}while(0)
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#define VB_PIC_BLK_SIZE(Width, Height, Type, size)\
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do{\
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unsigned int u32AlignWidth;\
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unsigned int u32AlignHeight;\
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unsigned int u32HeadSize;\
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u32AlignWidth = VB_ALIGN(Width, 16);\
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u32AlignHeight= VB_ALIGN(Height, 2);\
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u32HeadSize = VB_HEADER_STRIDE * u32AlignHeight;/* compress header stride 16 */\
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if (PIXEL_FORMAT_YUV_SEMIPLANAR_422 == Type)\
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{\
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size = (u32AlignWidth * u32AlignHeight + u32HeadSize) * 2;\
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}\
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else if (PIXEL_FORMAT_SINGLE == Type)\
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{\
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size = (u32AlignWidth * u32AlignHeight + u32HeadSize);\
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}\
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else\
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{\
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size = ((u32AlignWidth * u32AlignHeight + u32HeadSize) * 3) >> 1;\
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}\
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}while(0)
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#define VIU_GET_RAW_CHN(ViDev, RawChn)\
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do{\
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RawChn = VIU_MAX_CHN_NUM + ViDev;\
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}while(0)
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#ifdef __cplusplus
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#if __cplusplus
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}
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#endif
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#endif /* __cplusplus */
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#endif /* __HI_DEFINES_H__ */
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