26 lines
682 B
ReStructuredText
26 lines
682 B
ReStructuredText
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Change Log
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==========
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Next release
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------------
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v1.0 (December 20, 2022)
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------------------------
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* Initial release
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* Data structures ``aiger``, ``load``, ``bench``, ``verilog``, ``blif``
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* Logic synthesis commands ``balance``
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* Logic synthesis commands ``resub``
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* Logic resynthesis commands ``resyn``
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* Logic synthesis commands ``rewrite``
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* Logic synthesis commands ``reduction``
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* Logic synthesis commands ``refactor``
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* Compute truth table for expression ``exprsim``
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* Combinational equivalence checking for AIG network ``cec``
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* SAT solver ``sat``
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* Logic network simulation ``sim``
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* FPGA technology mapping of the network ``lutmap``
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* Standard cell mapping ``techmap``
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