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cutrw

noah v2.0
panhongyang 2023-08-03 09:42:26 +08:00
parent 275b6696f8
commit 3be82b9b0f
4 changed files with 72 additions and 136 deletions
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2
lib/mockturtle

@ -1 +1 @@
Subproject commit fac58aa217f7b4c4d5327b201f5e9fe8cbf9ee6a
Subproject commit a5a903a24d2c9cac711881cba6eb16972919f5d3

71
src/commands/cut_rewriting.hpp
View File

@ -33,6 +33,8 @@
#include <mockturtle/views/fanout_view.hpp>
#include "../core/misc.hpp"
#include "../networks/aoig/xag_lut_npn.hpp"
#include "../networks/stp/stp_npn.hpp"
using namespace std;
using namespace mockturtle;
@ -46,6 +48,10 @@ class rewrite_command : public command {
add_flag("--mig, -m", "rewriting for MIG");
add_flag("--xag, -g", "rewriting for XAG");
add_flag("--klut, -l", "rewriting for k-LUT");
add_flag("--klut_npn, -n", "cut rewriting based on k-LUT NPN network");
add_flag("--xag_npn_lut, -u",
"cut rewriting based on XAG NPN based LUT network");
add_flag("--xag_npn, -p", "cut rewriting based on XAG NPN network");
add_flag("--akers, -a", "Cut rewriting with Akers synthesis for MIG");
add_flag("--compatibility_graph, -c", "In-place cut rewriting");
add_flag("--verbose, -v", "print the information");
@ -148,6 +154,71 @@ class rewrite_command : public command {
store<klut_network>().extend();
store<klut_network>().current() = klut;
}
} else if (is_set("xag_npn_lut")) {
xag_network xag = store<xag_network>().current();
phyLS::print_stats(xag);
begin = clock();
xag_npn_lut_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
xag = cut_rewriting(xag, resyn, ps);
xag = cleanup_dangling(xag);
// bidecomposition refactoring
bidecomposition_resynthesis<xag_network> resyn2;
refactoring(xag, resyn2);
xag = cleanup_dangling(xag);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = cleanup_dangling(xag);
} else if (is_set("xag_npn")) {
xag_network xag = store<xag_network>().current();
phyLS::print_stats(xag);
begin = clock();
xag_npn_resynthesis<xag_network> resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
ps.min_cand_cut_size = 2;
ps.min_cand_cut_size_override = 3;
xag = cut_rewriting(xag, resyn, ps);
xag = cleanup_dangling(xag);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = cleanup_dangling(xag);
} else if (is_set("klut_npn")) {
klut_network klut = store<klut_network>().current();
phyLS::print_stats(klut);
begin = clock();
stp_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
ps.allow_zero_gain = false;
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(klut, resyn);
else
klut = cut_rewriting(klut, resyn, ps);
klut = cleanup_dangling(klut);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(klut);
store<klut_network>().extend();
store<klut_network>().current() = cleanup_dangling(klut);
} else {
if (store<aig_network>().size() == 0u)
std::cerr << "Error: Empty AIG network\n";

134
src/commands/cutrw.hpp
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@ -1,134 +0,0 @@
/* phyLS: Advanced Logic Synthesis and Optimization tool
* Copyright (C) 2019- Ningbo University, Ningbo, China */
/**
* @file cutrw.hpp
*
* @brief cut rewriting
*
* @author Zhufei Chu
* @since 0.1
*/
#ifndef CUTRW_HPP
#define CUTRW_HPP
#include <mockturtle/algorithms/node_resynthesis/bidecomposition.hpp>
#include <mockturtle/mockturtle.hpp>
#include "../core/misc.hpp"
#include "../networks/aoig/xag_lut_npn.hpp"
#include "../networks/stp/stp_npn.hpp"
using namespace std;
namespace alice {
class cutrw_command : public command {
public:
explicit cutrw_command(const environment::ptr& env)
: command(env, "Performs cut rewriting") {
add_flag("--xag_npn_lut,-g", "cut rewriting based on xag_npn_lut");
add_flag("--xag_npn,-p", "cut rewriting based on xag_npn");
add_flag("--klut_npn,-l", "cut rewriting based on klut_npn");
add_flag("--compatibility_graph, -c", "In-place cut rewriting");
}
void execute() {
clock_t begin, end;
double totalTime = 0.0;
begin = clock();
/* parameters */
if (is_set("xag_npn_lut")) {
xag_network xag = store<xag_network>().current();
phyLS::print_stats(xag);
xag_npn_lut_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
xag = cut_rewriting(xag, resyn, ps);
xag = cleanup_dangling(xag);
// bidecomposition refactoring
bidecomposition_resynthesis<xag_network> resyn2;
refactoring(xag, resyn2);
xag = cleanup_dangling(xag);
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = cleanup_dangling(xag);
} else if (is_set("xag_npn")) {
begin = clock();
xag_network xag = store<xag_network>().current();
phyLS::print_stats(xag);
xag_npn_resynthesis<xag_network> resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
ps.min_cand_cut_size = 2;
ps.min_cand_cut_size_override = 3;
xag = cut_rewriting(xag, resyn, ps);
xag = cleanup_dangling(xag);
phyLS::print_stats(xag);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
store<xag_network>().extend();
store<xag_network>().current() = cleanup_dangling(xag);
} else if (is_set("klut_npn")) {
klut_network klut = store<klut_network>().current();
phyLS::print_stats(klut);
stp_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
ps.allow_zero_gain = false;
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(klut, resyn);
else
klut = cut_rewriting(klut, resyn, ps);
klut = cleanup_dangling(klut);
phyLS::print_stats(klut);
store<klut_network>().extend();
store<klut_network>().current() = cleanup_dangling(klut);
} else {
xmg_network xmg = store<xmg_network>().current();
phyLS::print_stats(xmg);
xmg_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
xmg = cut_rewriting(xmg, resyn, ps);
xmg = cleanup_dangling(xmg);
phyLS::print_stats(xmg);
store<xmg_network>().extend();
store<xmg_network>().current() = cleanup_dangling(xmg);
}
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
cout.setf(ios::fixed);
cout << "[Total CPU time] : " << setprecision(3) << totalTime << " s"
<< endl;
}
private:
bool verbose = false;
};
ALICE_ADD_COMMAND(cutrw, "Synthesis")
} // namespace alice
#endif

1
src/phyLS.cpp
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@ -51,7 +51,6 @@
#include "commands/simulator.hpp"
#include "commands/abc/cec.hpp"
#include "commands/stpfr.hpp"
#include "commands/cutrw.hpp"
#include "commands/exact/exact_lut.hpp"
#include "commands/exact/lutrw.hpp"