version 4.0 lutmap

src/commands/algebraic_rewriting.hpp

@@ -0,0 +1,101 @@
+/* phyLS: powerful heightened yielded Logic Synthesis
+ * Copyright (C) 2022 */
+
+/**
+ * @file algebraic_rewriting.hpp
+ *
+ * @brief algebraic depth rewriting
+ *
+ * @author Homyoung
+ * @since  2022/12/14
+ */
+
+#ifndef ALGEBRAIC_REWRITING_HPP
+#define ALGEBRAIC_REWRITING_HPP
+
+#include <mockturtle/algorithms/mig_algebraic_rewriting.hpp>
+#include <mockturtle/algorithms/xag_algebraic_rewriting.hpp>
+#include <mockturtle/algorithms/xmg_algebraic_rewriting.hpp>
+#include <mockturtle/networks/mig.hpp>
+#include <mockturtle/networks/xag.hpp>
+#include <mockturtle/networks/xmg.hpp>
+#include <mockturtle/traits.hpp>
+#include <mockturtle/views/depth_view.hpp>
+
+using namespace std;
+using namespace mockturtle;
+
+namespace alice {
+
+class algebraic_rewriting_command : public command {
+ public:
+  explicit algebraic_rewriting_command(const environment::ptr& env)
+      : command(env, "algebraic depth rewriting [default = MIG]") {
+    add_flag("--xag, -g", "refactoring for XAG");
+    add_flag("--xmg, -x", "refactoring for XMG");
+    add_flag("--verbose, -v", "print the information");
+  }
+
+ protected:
+  void execute() {
+    clock_t begin, end;
+    double totalTime;
+
+    begin = clock();
+    if (is_set("xag")) {
+      if (store<xag_network>().size() == 0u)
+        std::cerr << "Error: Empty XAG network\n";
+      else {
+        auto xag = store<xag_network>().current();
+        depth_view depth_xag{xag};
+        xag_algebraic_depth_rewriting_params ps;
+        ps.allow_rare_rules = true;
+        xag_algebraic_depth_rewriting(depth_xag, ps);
+        depth_xag = cleanup_dangling(depth_xag);
+        phyLS::print_stats(depth_xag);
+        store<xag_network>().extend();
+        store<xag_network>().current() = depth_xag;
+      }
+    } else if (is_set("xmg")) {
+      if (store<xmg_network>().size() == 0u)
+        std::cerr << "Error: Empty XMG network\n";
+      else {
+        auto xmg = store<xmg_network>().current();
+        depth_view depth_xmg{xmg};
+        xmg_algebraic_depth_rewriting_params ps;
+        ps.strategy = xmg_algebraic_depth_rewriting_params::selective;
+        xmg_algebraic_depth_rewriting(depth_xmg, ps);
+        depth_xmg = cleanup_dangling(depth_xmg);
+        phyLS::print_stats(depth_xmg);
+        store<xmg_network>().extend();
+        store<xmg_network>().current() = depth_xmg;
+      }
+    } else {
+      if (store<mig_network>().size() == 0u)
+        std::cerr << "Error: Empty MIG network\n";
+      else {
+        auto mig = store<mig_network>().current();
+        depth_view depth_mig{mig};
+        mig_algebraic_depth_rewriting_params ps;
+        mig_algebraic_depth_rewriting(depth_mig, ps);
+        depth_mig = cleanup_dangling(depth_mig);
+        phyLS::print_stats(depth_mig);
+        store<mig_network>().extend();
+        store<mig_network>().current() = depth_mig;
+      }
+    }
+    end = clock();
+    totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
+
+    cout.setf(ios::fixed);
+    cout << "[CPU time]   " << setprecision(2) << totalTime << " s" << endl;
+  }
+
+ private:
+};
+
+ALICE_ADD_COMMAND(algebraic_rewriting, "Logic synthesis")
+
+}  // namespace alice
+
+#endif

src/commands/exprsim.hpp

@@ -69,7 +69,7 @@ class exprsim_command : public command {
   uint32_t max_num_vars = 0u;
 };
 
-ALICE_ADD_COMMAND(exprsim, "I/O")
+ALICE_ADD_COMMAND(exprsim, "Verification")
 
 }  // namespace alice
 

src/commands/lutmap.hpp

@@ -0,0 +1,138 @@
+/* phyLS: powerful heightened yielded Logic Synthesis
+ * Copyright (C) 2022 */
+
+/**
+ * @file lutmap.hpp
+ *
+ * @brief performs FPGA technology mapping of the network
+ *
+ * @author Homyoung
+ * @since  2022/12/21
+ */
+
+#ifndef LUTMAP_HPP
+#define LUTMAP_HPP
+
+#include <mockturtle/generators/arithmetic.hpp>
+#include <mockturtle/networks/aig.hpp>
+#include <mockturtle/traits.hpp>
+#include <mockturtle/views/mapping_view.hpp>
+
+#include "../core/lut_mapper.hpp"
+
+using namespace std;
+using namespace mockturtle;
+
+namespace alice {
+
+class lutmap_command : public command {
+ public:
+  explicit lutmap_command(const environment::ptr& env)
+      : command(env, "FPGA technology mapping of the network [default = AIG]") {
+    add_flag("--mig, -m", "FPGA technology mapping for MIG");
+    add_flag("--xag, -g", "FPGA technology mapping for XAG");
+    add_flag("--xmg, -x", "FPGA technology mapping for XMG");
+    add_option("--cut_size, -s", cut_size,
+               "Maximum number of leaves for a cut [default = 4]");
+    add_option(
+        "--cut_limit, -l", cut_limit,
+        "the input Maximum number of cuts for a node name [default = 25]");
+    add_option("--relax_required, -r", relax_required,
+               "delay relaxation ratio (%) [default = 0]");
+    add_flag("--area, -a", "toggles area-oriented mapping [default = false]");
+    add_flag("--recompute_cuts, -c",
+             "recompute cuts at each step [default = true]");
+    add_flag("--edge, -e", "Use edge count reduction [default = true]");
+    add_flag("--dominated_cuts, -d",
+             "Remove the cuts that are contained in others [default = true]");
+    add_flag("--verbose, -v", "print the information");
+  }
+
+ protected:
+  void execute() {
+    if (is_set("mig")) {
+      if (store<mig_network>().size() == 0u)
+        std::cerr << "Error: Empty MIG network\n";
+      else {
+        auto mig = store<mig_network>().current();
+        mapping_view mapped_mig{mig};
+        phyLS::lut_map_params ps;
+        if (is_set("area")) ps.area_oriented_mapping = true;
+        if (is_set("relax_required")) ps.relax_required = relax_required;
+        if (is_set("cut_size")) ps.cut_enumeration_ps.cut_size = cut_size;
+        if (is_set("cut_limit")) ps.cut_enumeration_ps.cut_limit = cut_limit;
+        if (is_set("recompute_cuts")) ps.recompute_cuts = false;
+        if (is_set("edge")) ps.edge_optimization = false;
+        if (is_set("dominated_cuts")) ps.remove_dominated_cuts = false;
+        cout << "Mapped MIG into " << cut_size << "-LUT : ";
+        phyLS::lut_map(mapped_mig, ps);
+        mapped_mig.clear_mapping();
+      }
+    } else if (is_set("xag")) {
+      if (store<xag_network>().size() == 0u)
+        std::cerr << "Error: Empty XAG network\n";
+      else {
+        auto xag = store<xag_network>().current();
+        mapping_view mapped_xag{xag};
+        phyLS::lut_map_params ps;
+        if (is_set("area")) ps.area_oriented_mapping = true;
+        if (is_set("relax_required")) ps.relax_required = relax_required;
+        if (is_set("cut_size")) ps.cut_enumeration_ps.cut_size = cut_size;
+        if (is_set("cut_limit")) ps.cut_enumeration_ps.cut_limit = cut_limit;
+        if (is_set("recompute_cuts")) ps.recompute_cuts = false;
+        if (is_set("edge")) ps.edge_optimization = false;
+        if (is_set("dominated_cuts")) ps.remove_dominated_cuts = false;
+        cout << "Mapped XAG into " << cut_size << "-LUT : ";
+        phyLS::lut_map(mapped_xag, ps);
+        mapped_xag.clear_mapping();
+      }
+    } else if (is_set("xmg")) {
+      if (store<xmg_network>().size() == 0u)
+        std::cerr << "Error: Empty XMG network\n";
+      else {
+        auto xmg = store<xmg_network>().current();
+        mapping_view mapped_xmg{xmg};
+        phyLS::lut_map_params ps;
+        if (is_set("area")) ps.area_oriented_mapping = true;
+        if (is_set("relax_required")) ps.relax_required = relax_required;
+        if (is_set("cut_size")) ps.cut_enumeration_ps.cut_size = cut_size;
+        if (is_set("cut_limit")) ps.cut_enumeration_ps.cut_limit = cut_limit;
+        if (is_set("recompute_cuts")) ps.recompute_cuts = false;
+        if (is_set("edge")) ps.edge_optimization = false;
+        if (is_set("dominated_cuts")) ps.remove_dominated_cuts = false;
+        cout << "Mapped XMG into " << cut_size << "-LUT : ";
+        phyLS::lut_map(mapped_xmg, ps);
+        mapped_xmg.clear_mapping();
+      }
+    } else {
+      if (store<aig_network>().size() == 0u)
+        std::cerr << "Error: Empty AIG network\n";
+      else {
+        auto aig = store<aig_network>().current();
+        mapping_view mapped_aig{aig};
+        phyLS::lut_map_params ps;
+        if (is_set("area")) ps.area_oriented_mapping = true;
+        if (is_set("relax_required")) ps.relax_required = relax_required;
+        if (is_set("cut_size")) ps.cut_enumeration_ps.cut_size = cut_size;
+        if (is_set("cut_limit")) ps.cut_enumeration_ps.cut_limit = cut_limit;
+        if (is_set("recompute_cuts")) ps.recompute_cuts = false;
+        if (is_set("edge")) ps.edge_optimization = false;
+        if (is_set("dominated_cuts")) ps.remove_dominated_cuts = false;
+        cout << "Mapped AIG into " << cut_size << "-LUT : ";
+        phyLS::lut_map(mapped_aig, ps);
+        mapped_aig.clear_mapping();
+      }
+    }
+  }
+
+ private:
+  uint32_t cut_size{6u};
+  uint32_t cut_limit{8u};
+  uint32_t relax_required{0u};
+};
+
+ALICE_ADD_COMMAND(lutmap, "Mapping")
+
+}  // namespace alice
+
+#endif

src/commands/techmap.hpp

@@ -26,9 +26,9 @@
 
 namespace alice {
 
-  class tech_mapping_command: public command {
+  class techmap_command: public command {
   public:
-    explicit tech_mapping_command(const environment::ptr& env)
+    explicit techmap_command(const environment::ptr& env)
       : command(env, "Standard cell mapping : using AIG as default") {
       add_flag("--xmg, -x", "Standard cell mapping for XMG");
       add_flag("--mig, -m", "Standard cell mapping for MIG");
@@ -137,7 +137,7 @@ namespace alice {
     }
   };
 
-  ALICE_ADD_COMMAND(tech_mapping, "Mapping")
+  ALICE_ADD_COMMAND(techmap, "Mapping")
 
 }  // namespace alice
 

src/phyLS.cpp

@@ -39,5 +39,6 @@
 #include "commands/cec.hpp"
 #include "commands/functional_reduction.hpp"
 #include "commands/convert_graph.hpp"
+#include "commands/lutmap.hpp"
 
 ALICE_MAIN(phyLS)