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Examples
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============
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All commands
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----------------------------------
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Input:
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.. code-block:: bash
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help
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Output:
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::
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Verification commands:
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cec exprsim sat sim
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Mapping commands:
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lut_mapping lutmap techmap
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Synthesis commands:
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balance create_graph reduction refactor
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resub resyn rewrite
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I/O commands:
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load read_aiger read_bench read_blif
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read_genlib read_verilog write_aiger write_bench
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write_blif write_dot write_genlib write_verilog
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General commands:
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alias convert current help
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print ps quit set
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show store
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For more details, simply add '-h' after command to see all options of this command.
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Synthesis of EPFL benchmarks
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----------------------------------
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In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk.
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.. .. code-black:: c++
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Input:
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.. code-block:: bash
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.. spec spec;
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.. spec.verbosity = 0;
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read_aiger ~/phyLS/benchmarks/adder.aig
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ps -a
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resub // any synthesis commands
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ps -a
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read_genlib ~/phyLS/src/mcnc.genlib
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techmap
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.. chain c;
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.. dynamic_truth_table x( 3 ), y( 3 ), z( 3 );
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.. create_nth_var( x, 0 );
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.. create_nth_var( y, 1 );
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.. create_nth_var( z, 2 );
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.. // The sum and carry functions represent the outputs of the
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.. // chain that we want to synthesize.
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.. auto const sum = x ^ y ^ z;
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.. auto const carry = ternary_majority( x, y, z );
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.. spec[0] = sum;
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.. spec[1] = carry;
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.. // Call the synthesizer with the specification we've constructed.
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.. auto const result = synthesize( spec, c );
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.. // Ensure that synthesis was successful.
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.. assert( result == success );
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.. // Simulate the synthesized circuit and ensure that it
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.. // computes the correct functions.
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.. auto sim_fs = c.simulate();
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.. assert( sim_fs[0] == sum );
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.. assert( sim_fs[1] == carry );
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.. In this example, we synthesize a Boolean chain for a full adder
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.. specified by the two Boolean functions `sum` and `carry`. We see how
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.. synthesis is invoked using the `synthesize` function that takes two
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.. parameters. The first parameter is the specification `spec`, the
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.. second parameter `c` references a chain. If synthesis is successful,
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.. the `synthesize` function returns `success` and stores the synthesized
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.. chain in `c`. Last but not least, we simulate the chain to ensure
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.. that it's output functions are equivalent to the specified functions
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.. of the full adder.
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.. Percy offers several different encodings and synthesis methods, and
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.. allows its users to select from various SAT solver backends. By
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.. default all engines use ABC's `bsat` solver backend [1]_
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.. (`SLV_BSAT2`), the SSV encoding (`ENC_SSV`), and the standard
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.. synthesis method (`SYNTH_STD`). Suppose that this particular
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.. combination is not suitable for our workflow. We can then easily
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.. customize the synthesis process by cherry-picking a solver, encoder,
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.. and synthesis method from the available options.
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.. The next example demonstrates fence-based synthesis using the
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.. corresponding encoder and synthesis method together with ABC's `bsat`
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.. as solver backend:
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.. .. code-black:: c++
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.. percy::SolverType solver_type = percy::SLV_BSAT2;
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.. percy::EncoderType encoder_type = percy::ENC_FENCE;
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.. percy::SynthMethod synth_method = percy::SYNTH_FENCE;
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.. auto solver = get_solver( solver_type );
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.. auto encoder = get_encoder( *solver, encoder_type );
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.. auto const result = synthesize( spec, c, *solver, *encoder, synth_method );
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.. Enumerate (and count) partial DAGs
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.. ----------------------------------
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.. In the following code snippet, we use `percy` to enumerate partial
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.. DAGs for a given number of nodes (up to 7 nodes), count them, and
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.. print the numbers.
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.. .. code-black:: c++
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.. #include <percy/partial_dag.hpp>
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.. for ( auto i = 1u; i < 8; ++i )
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.. {
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.. const auto dags = percy::pd_generate( i );
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.. std::cout << i << ' ' << dags.size() << std::endl;
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.. }
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.. .. [1] https://github.com/berkeley-abc/abc
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Output:
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::
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$ AIG i/o = 256/129 gates = 1020 level = 255
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$ ntk i/o = 256/129 gates = 893 level = 256
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[CPU time] 0.09 s
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$ Mapped AIG into #gates = 701 area = 1849.00 delay = 204.90
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