From 90b00aa4bc4f29077e08faa5facb8fe07e5e4432 Mon Sep 17 00:00:00 2001
From: panhongyang <dulupao@126.com>
Date: Thu, 3 Aug 2023 10:03:27 +0800
Subject: [PATCH] docs

---
 docs/changelog.rst | 22 ++++++++++++++++++++++
 docs/examples.rst  | 21 +++++++++++++++------
 2 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/docs/changelog.rst b/docs/changelog.rst
index b5bd1aa..65cd7c1 100644
--- a/docs/changelog.rst
+++ b/docs/changelog.rst
@@ -4,6 +4,28 @@ Change Log
 Next release
 ------------
 
+v2.0 (August 03, 2023)
+------------------------
+
+* Semi-tensor product (STP) based k-LUT network simulation ``simulator``, which is faster than ``sim``
+* k-LUT network mapping ``lut_mapping``, default 4-LUT
+* NPN based network Logic synthesis ``rewrite``, faster and more efficient
+* STP-based functional reduction ``stpfr``
+* Logic synthesis commands ``fr``
+
+* Exact synthesis to find optimal 2-LUTs commands ``exact``
+* 2-LUT rewriting commands ``lutrw``, which enable technology dependent rewriting
+
+* ABC Logic synthesis commands ``aresub``
+* ABC Logic synthesis commands ``fraig``
+* ABC Logic synthesis commands ``strash``
+* ABC Logic synthesis commands ``comb``
+* ABC Logic synthesis commands ``acec``
+* ABC GIA Logic synthesis commands ``Afraig``
+* ABC GIA Logic synthesis commands ``Aget``
+
+* convert store element into ABC store ``convert``, which implement conversion between different data structures
+
 v1.0 (December 20, 2022)
 ------------------------
 
diff --git a/docs/examples.rst b/docs/examples.rst
index 9a833cc..a7ed551 100644
--- a/docs/examples.rst
+++ b/docs/examples.rst
@@ -11,20 +11,29 @@ Input:
 
 Output:
 ::
+    ABC commands:
+     aresub           comb             fraig            strash
+
     Verification commands:
-     cec              exprsim          sat              sim
+     acec             cec              exprsim          sat
+     sim              simulator
 
     Mapping commands:
      lut_mapping      lutmap           techmap
 
     Synthesis commands:
-     balance          create_graph     reduction        refactor
-     resub            resyn            rewrite
+     balance          create_graph     exact            fr
+     lutrw            refactor         resub            resyn
+     rewrite          stpfr
 
     I/O commands:
-     load             read_aiger       read_bench       read_blif
-     read_genlib      read_verilog     write_aiger      write_bench
-     write_blif       write_dot        write_genlib     write_verilog
+     load             read             read_aiger       read_bench
+     read_blif        read_genlib      read_gia         read_verilog
+     write            write_aiger      write_bench      write_blif
+     write_dot        write_genlib     write_gia        write_verilog
+
+    Gia commands:
+     Afraig           Aget
 
     General commands:
      alias            convert          current          help