documentation
parent
89137f5077
commit
d724f7eea6
|
@ -58,7 +58,7 @@ PROJECT_LOGO =
|
|||
# entered, it will be relative to the location where doxygen was started. If
|
||||
# left blank the current directory will be used.
|
||||
|
||||
OUTPUT_DIRECTORY =
|
||||
OUTPUT_DIRECTORY = doxyxml
|
||||
|
||||
# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
|
||||
# directories (in 2 levels) under the output directory of each output format and
|
||||
|
|
|
@ -0,0 +1,25 @@
|
|||
Change Log
|
||||
==========
|
||||
|
||||
Next release
|
||||
------------
|
||||
|
||||
v1.0 (December 20, 2022)
|
||||
------------------------
|
||||
|
||||
* Initial release
|
||||
* Data structures ``aiger``, ``load``, ``bench``, ``verilog``, ``blif``
|
||||
* Logic synthesis commands ``balance``
|
||||
* Logic synthesis commands ``resub``
|
||||
* Logic resynthesis commands ``resyn``
|
||||
* Logic synthesis commands ``rewrite``
|
||||
* Logic synthesis commands ``reduction``
|
||||
* Logic synthesis commands ``refactor``
|
||||
|
||||
* Compute truth table for expression ``exprsim``
|
||||
* Combinational equivalence checking for AIG network ``cec``
|
||||
* SAT solver ``sat``
|
||||
* Logic network simulation ``sim``
|
||||
|
||||
* FPGA technology mapping of the network ``lutmap``
|
||||
* Standard cell mapping ``techmap``
|
|
@ -2,7 +2,7 @@ Examples
|
|||
============
|
||||
|
||||
All commands
|
||||
----------------------------------
|
||||
----------------
|
||||
|
||||
Input:
|
||||
::
|
||||
|
@ -34,7 +34,7 @@ Output:
|
|||
For more details, simply add '-h' after command to see all options of this command.
|
||||
|
||||
Synthesis of EPFL benchmarks
|
||||
----------------------------------
|
||||
----------------
|
||||
|
||||
In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk.
|
||||
|
||||
|
|
|
@ -3,10 +3,39 @@ Welcome to phyLS's documentation!
|
|||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Contents:
|
||||
:caption: Contents
|
||||
|
||||
introduction
|
||||
installation
|
||||
changelog
|
||||
examples
|
||||
acknowledgments
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Reference
|
||||
|
||||
load
|
||||
read
|
||||
write
|
||||
balance
|
||||
create_graph
|
||||
reduction
|
||||
refactor
|
||||
resub
|
||||
resyn
|
||||
rewrite
|
||||
lut_mapping
|
||||
lutmap
|
||||
techmap
|
||||
cec
|
||||
exprsim
|
||||
sat
|
||||
sim
|
||||
|
||||
Indices and tables
|
||||
==================
|
||||
|
||||
.. * :ref:`genindex`
|
||||
.. * :ref:`modindex`
|
||||
.. * :ref:`search`
|
|
@ -1 +1,2 @@
|
|||
breathe
|
||||
sphinx==4.0.2
|
||||
breathe==4.30.0
|
||||
|
|
Loading…
Reference in New Issue