Change Log
==========

Next release
------------

v1.0 (December 20, 2022)
------------------------

* Initial release
* Data structures ``aiger``, ``load``, ``bench``, ``verilog``, ``blif``
* Logic synthesis commands ``balance``
* Logic synthesis commands ``resub``
* Logic resynthesis commands ``resyn``
* Logic synthesis commands ``rewrite``
* Logic synthesis commands ``reduction``
* Logic synthesis commands ``refactor``

* Compute truth table for expression ``exprsim``
* Combinational equivalence checking for AIG network ``cec``
* SAT solver ``sat``
* Logic network simulation ``sim``

* FPGA technology mapping of the network ``lutmap``
* Standard cell mapping ``techmap``