48 lines
1.6 KiB
ReStructuredText
48 lines
1.6 KiB
ReStructuredText
Change Log
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==========
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Next release
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------------
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v2.0 (August 03, 2023)
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------------------------
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* Semi-tensor product (STP) based k-LUT network simulation ``simulator``, which is faster than ``sim``
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* k-LUT network mapping ``lut_mapping``, default 4-LUT
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* NPN based network Logic synthesis ``rewrite``, faster and more efficient
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* STP-based functional reduction ``stpfr``
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* Logic synthesis commands ``fr``
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* Exact synthesis to find optimal 2-LUTs commands ``exact``
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* 2-LUT rewriting commands ``lutrw``, which enable technology dependent rewriting
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* ABC Logic synthesis commands ``aresub``
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* ABC Logic synthesis commands ``fraig``
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* ABC Logic synthesis commands ``strash``
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* ABC Logic synthesis commands ``comb``
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* ABC Logic synthesis commands ``acec``
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* ABC GIA Logic synthesis commands ``Afraig``
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* ABC GIA Logic synthesis commands ``Aget``
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* convert store element into ABC store ``convert``, which implement conversion between different data structures
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v1.0 (December 20, 2022)
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* Initial release
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* Data structures ``aiger``, ``load``, ``bench``, ``verilog``, ``blif``
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* Logic synthesis commands ``balance``
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* Logic synthesis commands ``resub``
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* Logic resynthesis commands ``resyn``
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* Logic synthesis commands ``rewrite``
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* Logic synthesis commands ``reduction``
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* Logic synthesis commands ``refactor``
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* Compute truth table for expression ``exprsim``
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* Combinational equivalence checking for AIG network ``cec``
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* SAT solver ``sat``
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* Logic network simulation ``sim``
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* FPGA technology mapping of the network ``lutmap``
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* Standard cell mapping ``techmap``
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