A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

logic-synthesis

Go to file

panhongyang 90b00aa4bc docs		2023-08-03 10:03:27 +08:00
benchmarks	EPFL benchmarks	2022-12-14 01:35:54 -05:00
docs	docs	2023-08-03 10:03:27 +08:00
lib	cutrw	2023-08-03 09:42:26 +08:00
src	cutrw	2023-08-03 09:42:26 +08:00
.gitignore	Initial commit	2022-12-14 08:51:36 +08:00
.gitmodules	update for exact synthesis	2023-08-02 18:08:30 +08:00
CMakeLists.txt	update version 0.4	2023-03-02 13:34:02 +08:00
LICENSE	Initial commit	2022-12-14 08:51:36 +08:00
README.md	Update README.md	2023-03-14 21:07:43 +08:00

README.md

powerful heightened yielded Logic Synthesis (phyLS)

phyLS is based on the mockturtle and the abc, it can optimize different logics attributes. Currently, it supports mockturtle format(AIG, MIG, XAG, XMG) and abc format(AIG,GIA) based optimization.

Read the documentation here.

Requirements

A modern compiler is required to build the libraries. Compiled successfully with Clang 6.0.1, Clang 12.0.0, GCC 7.3.0, and GCC 8.2.0.

How to Compile

git clone --recursive https://github.com/panhongyang0/phyLS.git
cd phyLS
mkdir build
cd build
cmake ..
make
./bin/phyLS