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pluto_hdl_adi/docs/regmap/adi_regmap_spi_engine.txt

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docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
TITLE
SPI Engine (axi_spi_engine)
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
AXI_SPI_ENGINE
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDTITLE
############################################################################################
############################################################################################
REG
0x00
VERSION
SPI Engine: create inverted CS mode (#1301) SPI Engine: create inverted CS mode Add a CS Invert Mask instruction for selecting the polarity of the Chip Select pins. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-05-08 14:19:37 +00:00
Version of the peripheral. Follows semantic versioning. Current version 1.02.00.
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDREG
FIELD
SPI Engine: create inverted CS mode (#1301) SPI Engine: create inverted CS mode Add a CS Invert Mask instruction for selecting the polarity of the Chip Select pins. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-05-08 14:19:37 +00:00
[31:16] 0x00000001
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
VERSION_MAJOR
RO
ENDFIELD
FIELD
SPI Engine: create inverted CS mode (#1301) SPI Engine: create inverted CS mode Add a CS Invert Mask instruction for selecting the polarity of the Chip Select pins. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-05-08 14:19:37 +00:00
[15:8] 0x00000002
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
VERSION_MINOR
RO
ENDFIELD
FIELD
SPI Engine: create inverted CS mode (#1301) SPI Engine: create inverted CS mode Add a CS Invert Mask instruction for selecting the polarity of the Chip Select pins. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-05-08 14:19:37 +00:00
[7:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
VERSION_PATCH
RO
ENDFIELD
############################################################################################
############################################################################################
REG
0x01
PERIPHERAL_ID
ENDREG
FIELD
[31:0] ''ID''
PERIPHERAL_ID
RO
Value of the ID configuration parameter.
In case of multiple instances, each instance will have a unique ID.
ENDFIELD
############################################################################################
############################################################################################
REG
0x02
SCRATCH
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SCRATCH
RW
Scratch register useful for debug.
ENDFIELD
############################################################################################
############################################################################################
REG
0x03
DATA_WIDTH
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[7:4] ''NUM_OF_SDI''
NUM_OF_SDI
RO
Number of SDI.
It is equal with the maximum supported SDI lines in bits.
ENDFIELD
FIELD
[3:0] ''DATA_WITH''
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DATA_WIDTH
RO
Data width of the SDI/SDO parallel interface.
It is equal with the maximum supported transfer length in bits.
ENDFIELD
############################################################################################
############################################################################################
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
REG
0x04
OFFLOAD_MEM_ADDR_WIDTH
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:8] 0x00000004
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
SDO_MEM_ADDRESS_WIDTH
RO
Address width for the data (SDO) memory on the Offload Module.
The size of the memory is thus ``2**SDO_MEM_ADDRESS_WIDTH`` data words.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000004
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
CMD_MEM_ADDRESS_WIDTH
RO
Address width for the command memory on the Offload Module.
The size of the command memory is thus ``2**CMD_MEM_ADDRESS_WIDTH`` instructions.
ENDFIELD
############################################################################################
############################################################################################
REG
0x05
FIFO_ADDR_WIDTH
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:24] 0x00000005
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
SDI_FIFO_ADDRESS_WIDTH
RO
Address width for the SDI FIFO.
The size of the SDI FIFO is thus ``2**SDI_FIFO_ADDRESS_WIDTH``.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[23:16] 0x00000005
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
SDO_FIFO_ADDRESS_WIDTH
RO
Address width for the SDO FIFO.
The size of the SDO FIFO is thus ``2**SDO_FIFO_ADDRESS_WIDTH``.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:8] 0x00000004
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
SYNC_FIFO_ADDRESS_WIDTH
RO
Address width for the synchronization FIFO.
The size of the synchronization FIFO is thus ``2**SYNC_FIFO_ADDRESS_WIDTH``.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000004
SPI Engine: Add registers for Offload memory and FIFO sizes (#1279) * SPI Engine: Add registers for Offload memory and FIFO sizes Adds registers at dword 0x04 and 0x05, respectively allowing software to get the sizes of the Offload Module memories (command and sdo) or the sizes of the FIFOs on the AXI regmap. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-03-08 11:40:48 +00:00
CMD_FIFO_ADDRESS_WIDTH
RO
Address width for the command FIFO.
The size of the command FIFO is thus ``2**CMD_FIFO_ADDRESS_WIDTH``.
ENDFIELD
############################################################################################
############################################################################################
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
REG
0x10
ENABLE
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000001
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENABLE
RW
Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset.
For proper operation, the bit needs to be set to 0.
ENDFIELD
############################################################################################
############################################################################################
REG
0x20
IRQ_MASK
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
CMD_ALMOST_EMPTY
RW
If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDO_ALMOST_EMPTY
RW
If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[2] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDI_ALMOST_FULL
RW
If set to 0 the SDI_ALMOST_FULL interrupt is masked.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[3] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SYNC_EVENT
RW
If set to 0 the SYNC_EVENT interrupt is masked.
ENDFIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[4] 0x00000000
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
OFFLOAD_SYNC_ID_PENDING
RW
If set to 0 the OFFLOAD_SYNC_ID_PENDING interrupt is masked.
ENDFIELD
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
############################################################################################
############################################################################################
REG
0x21
IRQ_PENDING
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
IRQ_PENDING
RW1C
Pending IRQs with mask.
ENDFIELD
############################################################################################
############################################################################################
REG
0x22
IRQ_SOURCE
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
IRQ_SOURCE
RO
Pending IRQs without mask.
ENDFIELD
############################################################################################
############################################################################################
REG
0x30
SYNC_ID
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SYNC_ID
RO
Last synchronization event ID received from the SPI engine control interface.
ENDFIELD
############################################################################################
############################################################################################
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
REG
0x31
OFFLOAD_SYNC_ID
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
OFFLOAD_SYNC_ID
RO
Offload Sync ID.
ENDFIELD
############################################################################################
############################################################################################
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
REG
0x34
CMD_FIFO_ROOM
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] log2((2^''CMD_FIFO_ADDRESS_WIDTH'')-1)
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
CMD_FIFO_ROOM
RO
Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register
depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
ENDFIELD
############################################################################################
############################################################################################
REG
0x35
SDO_FIFO_ROOM
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] log2((2^''SDO_FIFO_ADDRESS_WIDTH'')-1)
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDO_FIFO_ROOM
RO
Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM
register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
ENDFIELD
############################################################################################
############################################################################################
REG
0x36
SDI_FIFO_LEVEL
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDI_FIFO_LEVEL
RO
Number of valid entries in the serial-data-in FIFO.
ENDFIELD
############################################################################################
############################################################################################
REG
0x38
CMD_FIFO
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
CMD_FIFO
WO
Command FIFO register. Writing to this register inserts an entry into the command FIFO.
Writing to this register when the command FIFO is full has no effect and the written entry
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
is discarded. Reading from this register always returns 0x0.
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
0x39
SDO_FIFO
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDO_FIFO
WO
SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO.
Writing to this register when the SDO FIFO is full has no effect and the written entry is
regmap: Update SPI Engine regmap
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discarded. Reading from this register always returns 0x0.
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
0x3a
SDI_FIFO
ENDREG
FIELD
regmap: Update SPI Engine regmap
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[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDI_FIFO
RO
SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO.
Reading this register when the SDI FIFO is empty will return undefined data.
Writing to it has no effect.
ENDFIELD
############################################################################################
############################################################################################
regmap: Update SPI Engine regmap
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REG
0x3b
SDI_FIFO_MSB
ENDREG
FIELD
[31:0] 0xXXXXXXXX
SDI_FIFO_MSB
RO
Store SDI's 32 bits MSB, if exists.
ENDFIELD
############################################################################################
############################################################################################
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
REG
0x3c
SDI_FIFO_PEEK
ENDREG
FIELD
regmap: Update SPI Engine regmap
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[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDI_FIFO_PEEK
RO
SDI FIFO peek register.
Reading from this register returns the first entry from the SDI FIFO, but without removing
it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined
data. Writing to it has no effect.
ENDFIELD
############################################################################################
############################################################################################
REG
0x40
OFFLOAD0_EN
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
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OFFLOAD0_EN
RW
Set this bit to enable the offload module.
ENDFIELD
############################################################################################
############################################################################################
REG
0x41
OFFLOAD0_STATUS
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
OFFLOAD0_STATUS
RO
Offload status register.
ENDFIELD
############################################################################################
############################################################################################
REG
0x42
OFFLOAD0_MEM_RESET
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
OFFLOAD0_MEM_RESET
WO
Reset the memory of the offload module.
ENDFIELD
############################################################################################
############################################################################################
REG
0x44
OFFLOAD0_CDM_FIFO
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
OFFLOAD0_CDM_FIFO
WO
Offload command FIFO register. Writing to this register inserts an entry into the command FIFO
of the offload module. Writing to this register when the command FIFO is full has no effect
regmap: Update SPI Engine regmap
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and the written entry is discarded. Reading from this register always returns 0x0.
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
0x45
OFFLOAD0_SDO_FIFO
ENDREG
FIELD
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
[31:0] 0xXXXXXXXX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
OFFLOAD0_SDO_FIFO
WO
Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO.
Writing to this register when the SDO FIFO is full has no effect and the written entry is
regmap: Update SPI Engine regmap
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discarded. Reading from this register always returns 0x0.
ENDFIELD
############################################################################################
############################################################################################
REG
0x80
CFG_INFO_0
ENDREG
FIELD
[31:0] ''CFG_INFO_0''
CFG_INFO_0
RO
Configuration Info.
ENDFIELD
############################################################################################
############################################################################################
REG
0x81
CFG_INFO_1
ENDREG
FIELD
[31:0] ''CFG_INFO_1''
CFG_INFO_1
RO
Configuration Info.
ENDFIELD
############################################################################################
############################################################################################
REG
0x82
CFG_INFO_2
ENDREG
FIELD
[31:0] ''CFG_INFO_2''
CFG_INFO_2
RO
Configuration Info.
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
regmap: Update SPI Engine regmap
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############################################################################################
############################################################################################
REG
0x83
CFG_INFO_3
ENDREG
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
regmap: Update SPI Engine regmap
2024-03-20 11:53:03 +00:00
FIELD
[31:0] ''CFG_INFO_3''
CFG_INFO_4
RO
Configuration Info.
ENDFIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
############################################################################################
############################################################################################