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docs/user_guide: Add user guide documentation * Created the first level of pages for the User guide, from Analog Wiki: * Architecture * Build HDL * Customize HDL * Docs guidelines (edited) * Git repository * HDL coding guideline (edited) * Introduction * IP cores * Porting projects (edited) * Releases * Third party * Moved hdl_coding_guideline under user_guide and changed extension to rst * Deleted hdl_pr_process.md * docs_guideline: Add reference to project doc template * porting_project: Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-20 13:04:46 +00:00
.. _introduction:
Introduction
===============================================================================
The main purpose of this user guide is to help the user understand and use
(modify or otherwise) the HDL resources provided by `Analog Devices, Inc.`_,
and to provide advices and instructions for using these resources.
These resources are found on the GitHub, the
docs: links, drop part, fixups, codeowners Drop part role, use generic adi instead for root adi domain links. For future reference, the snipped used was: find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \; Drop Containerfile. Add option to validate links status (e.g. 200, 404), intended mostly for CI use to check if a page has disappeared from the internet. Validate links uses coroutines to launch multiple tasks concurrently, but do it in bundles to avoid being rate limited. Fixup regmap styling. Add imoldovan, jmarques, spop, lbarbosa as docs codeowners. Remove branch field for links to the hdl repo. Change git role to display full path. Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link in ad716_sdz project. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
:git-hdl:`/`.
docs/user_guide: Add user guide documentation * Created the first level of pages for the User guide, from Analog Wiki: * Architecture * Build HDL * Customize HDL * Docs guidelines (edited) * Git repository * HDL coding guideline (edited) * Introduction * IP cores * Porting projects (edited) * Releases * Third party * Moved hdl_coding_guideline under user_guide and changed extension to rst * Deleted hdl_pr_process.md * docs_guideline: Add reference to project doc template * porting_project: Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-20 13:04:46 +00:00
After reading this guide, the user should be able to build a specific project
docs: links, drop part, fixups, codeowners Drop part role, use generic adi instead for root adi domain links. For future reference, the snipped used was: find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \; Drop Containerfile. Add option to validate links status (e.g. 200, 404), intended mostly for CI use to check if a page has disappeared from the internet. Validate links uses coroutines to launch multiple tasks concurrently, but do it in bundles to avoid being rate limited. Fixup regmap styling. Add imoldovan, jmarques, spop, lbarbosa as docs codeowners. Remove branch field for links to the hdl repo. Change git role to display full path. Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link in ad716_sdz project. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
from the :git-hdl:`/` and be able to modify
docs/user_guide: Add user guide documentation * Created the first level of pages for the User guide, from Analog Wiki: * Architecture * Build HDL * Customize HDL * Docs guidelines (edited) * Git repository * HDL coding guideline (edited) * Introduction * IP cores * Porting projects (edited) * Releases * Third party * Moved hdl_coding_guideline under user_guide and changed extension to rst * Deleted hdl_pr_process.md * docs_guideline: Add reference to project doc template * porting_project: Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-20 13:04:46 +00:00
(if so desire) the digital data path implemented in the FPGA.
Furthermore, all ADI developed and supported IPs are presented in detail.
At the same time, this user guide does not intend to be a guide for any third
party tool. To understand and use the HDL framework efficiently the user needs
to have a **solid understanding on how an FPGA works, to be familiar with all
the design tools and flows**.
If somebody does not have this knowledge we highly recommend to make some
general research and go through some basic tutorials with the targeted
development platform. At the vendor's support pages you can find an abundance
of information:
* `AMD Xilinx support`_
* `Intel support`_
.. _Analog Devices, Inc.: https://www.analog.com/en/index.html
.. _AMD Xilinx support: https://www.xilinx.com/support.html
.. _Intel support: https://www.intel.com/content/www/us/en/programmable/support/support-resources.html