pluto_hdl_adi/library/util_cdc/sync_data.v

// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
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//      This will allow to generate bit files and not release the source code,
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//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module sync_data #(
  parameter NUM_OF_BITS = 1,
  parameter ASYNC_CLK = 1
) (
  input in_clk,
  input [NUM_OF_BITS-1:0] in_data,
  input out_clk,
  output reg [NUM_OF_BITS-1:0] out_data
);

  generate
  if (ASYNC_CLK == 1) begin

  wire out_toggle;
  wire in_toggle;

  reg out_toggle_d1 = 1'b0;
  reg in_toggle_d1 = 1'b0;

  reg [NUM_OF_BITS-1:0] cdc_hold;

  sync_bits i_sync_out (
    .in_bits(in_toggle_d1),
    .out_clk(out_clk),
    .out_resetn(1'b1),
    .out_bits(out_toggle));

  sync_bits i_sync_in (
    .in_bits(out_toggle_d1),
    .out_clk(in_clk),
    .out_resetn(1'b1),
    .out_bits(in_toggle));

  wire in_load = in_toggle == in_toggle_d1;
  wire out_load = out_toggle ^ out_toggle_d1;

  always @(posedge in_clk) begin
    if (in_load == 1'b1) begin
      cdc_hold <= in_data;
      in_toggle_d1 <= ~in_toggle_d1;
    end
  end

  always @(posedge out_clk) begin
    if (out_load == 1'b1) begin
      out_data <= cdc_hold;
    end
    out_toggle_d1 <= out_toggle;
  end

  end else begin
    always @(*) begin
      out_data <= in_data;
    end
  end
  endgenerate

endmodule