164 lines
5.2 KiB
Tcl
164 lines
5.2 KiB
Tcl
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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set LVDS_CMOS_N $ad_project_params(LVDS_CMOS_N)
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# ad4858 interface
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if {$LVDS_CMOS_N == "0"} {
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create_bd_port -dir O scki
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create_bd_port -dir I scko
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create_bd_port -dir I adc_lane_0
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create_bd_port -dir I adc_lane_1
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create_bd_port -dir I adc_lane_2
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create_bd_port -dir I adc_lane_3
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create_bd_port -dir I adc_lane_4
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create_bd_port -dir I adc_lane_5
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create_bd_port -dir I adc_lane_6
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create_bd_port -dir I adc_lane_7
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} else {
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create_bd_port -dir O scki_p
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create_bd_port -dir O scki_n
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create_bd_port -dir I scko_p
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create_bd_port -dir I scko_n
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create_bd_port -dir I sdo_p
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create_bd_port -dir I sdo_n
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}
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create_bd_port -dir I busy
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create_bd_port -dir O cnv
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create_bd_port -dir O lvds_cmos_n
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create_bd_port -dir O system_cpu_clk
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# adc clock generator
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ad_ip_instance axi_clkgen adc_clkgen
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ad_ip_parameter adc_clkgen CONFIG.CLKIN_PERIOD 5
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ad_ip_parameter adc_clkgen CONFIG.VCO_DIV 1
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ad_connect sys_200m_clk adc_clkgen/clk
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if {$LVDS_CMOS_N == "0"} {
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# CMOS setup
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# clk0 = 100M
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ad_ip_parameter adc_clkgen CONFIG.VCO_MUL 5
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ad_ip_parameter adc_clkgen CONFIG.CLK0_DIV 10
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ad_connect adc_clk adc_clkgen/clk_0
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} else {
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# LVDS setup
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# clk0 = 200M
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# clk1 = 400M
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ad_ip_parameter adc_clkgen CONFIG.VCO_MUL 6
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ad_ip_parameter adc_clkgen CONFIG.CLK0_DIV 6
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ad_ip_parameter adc_clkgen CONFIG.ENABLE_CLKOUT1 "true"
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ad_ip_parameter adc_clkgen CONFIG.CLK1_DIV 3
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ad_connect adc_clk adc_clkgen/clk_0
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ad_connect adc_fast_clk adc_clkgen/clk_1
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}
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# adc clock domain reset
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ad_ip_instance proc_sys_reset adc_rstgen
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ad_ip_parameter adc_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_connect adc_rstgen/ext_reset_in sys_cpu_resetn
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ad_connect adc_rstgen/slowest_sync_clk adc_clk
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ad_connect adc_resetn adc_rstgen/peripheral_aresetn
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ad_connect adc_reset adc_rstgen/peripheral_reset
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# adc(ad4858-dma)
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ad_ip_instance axi_dmac ad4858_dma
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ad_ip_parameter ad4858_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter ad4858_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter ad4858_dma CONFIG.CYCLIC 0
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ad_ip_parameter ad4858_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter ad4858_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter ad4858_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter ad4858_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter ad4858_dma CONFIG.DMA_DATA_WIDTH_SRC 256
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ad_ip_parameter ad4858_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect adc_clk ad4858_dma/fifo_wr_clk
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# axi pwm gen
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ad_ip_instance axi_pwm_gen axi_pwm_gen
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ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 1
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1
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ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8
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ad_connect cnv axi_pwm_gen/pwm_0
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ad_connect adc_clk axi_pwm_gen/ext_clk
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ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
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ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
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# axi_ad4858
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ad_ip_instance axi_ad4858 axi_ad4858
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ad_ip_parameter axi_ad4858 CONFIG.LVDS_CMOS_N $LVDS_CMOS_N
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ad_ip_parameter axi_ad4858 CONFIG.EXTERNAL_CLK 1
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ad_connect axi_ad4858/external_clk adc_clk
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if {$LVDS_CMOS_N == "0"} {
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ad_connect adc_lane_0 axi_ad4858/lane_0
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ad_connect adc_lane_1 axi_ad4858/lane_1
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ad_connect adc_lane_2 axi_ad4858/lane_2
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ad_connect adc_lane_3 axi_ad4858/lane_3
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ad_connect adc_lane_4 axi_ad4858/lane_4
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ad_connect adc_lane_5 axi_ad4858/lane_5
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ad_connect adc_lane_6 axi_ad4858/lane_6
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ad_connect adc_lane_7 axi_ad4858/lane_7
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ad_connect scko axi_ad4858/scko
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ad_connect scki axi_ad4858/scki
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} else {
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ad_connect axi_ad4858/external_fast_clk adc_fast_clk
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ad_connect sdo_p axi_ad4858/sdo_p
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ad_connect sdo_n axi_ad4858/sdo_n
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ad_connect scko_p axi_ad4858/scko_p
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ad_connect scko_n axi_ad4858/scko_n
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ad_connect scki_p axi_ad4858/scki_p
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ad_connect scki_n axi_ad4858/scki_n
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}
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ad_connect busy axi_ad4858/busy
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ad_connect lvds_cmos_n axi_ad4858/lvds_cmos_n
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# adc-path channel pack
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ad_ip_instance util_cpack2 ad4858_adc_pack
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ad_ip_parameter ad4858_adc_pack CONFIG.NUM_OF_CHANNELS 8
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ad_ip_parameter ad4858_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
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ad_connect adc_clk ad4858_adc_pack/clk
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ad_connect adc_reset ad4858_adc_pack/reset
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ad_connect axi_ad4858/adc_valid ad4858_adc_pack/fifo_wr_en
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ad_connect ad4858_adc_pack/packed_fifo_wr ad4858_dma/fifo_wr
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ad_connect ad4858_adc_pack/fifo_wr_overflow axi_ad4858/adc_dovf
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for {set i 0} {$i < 8} {incr i} {
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ad_connect axi_ad4858/adc_data_$i ad4858_adc_pack/fifo_wr_data_$i
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ad_connect axi_ad4858/adc_enable_$i ad4858_adc_pack/enable_$i
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}
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ad_connect sys_cpu_clk system_cpu_clk
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ad_connect sys_200m_clk axi_ad4858/delay_clk
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ad_connect axi_pwm_gen/pwm_0 axi_ad4858/cnvs
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# interrupts
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ad_cpu_interrupt ps-10 mb-10 ad4858_dma/irq
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# cpu / memory interconnects
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ad_cpu_interconnect 0x43c00000 axi_ad4858
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ad_cpu_interconnect 0x43d00000 axi_pwm_gen
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ad_cpu_interconnect 0x43e00000 ad4858_dma
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ad_cpu_interconnect 0x44000000 adc_clkgen
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_dma_clk ad4858_dma/m_dest_axi
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ad_connect $sys_dma_resetn ad4858_dma/m_dest_axi_aresetn
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