2023-07-10 08:36:06 +00:00
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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2021-01-20 15:58:39 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name ref_clk [get_ports {fpga_refclk_in}]
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create_clock -period "4.000 ns" -name device_clk [get_ports {clkin6}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
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set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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