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pluto_hdl_adi/projects/cn0561/coraz7s/Makefile

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Makefile
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cn0561_coraz7s: Initial commit Because the inferface signals which pass through the eval board's Arduino connector are connected to level shifters the design will not work at the maximum clk frequency of 48MHz. The maximum tested frequency is 24MHz.
2022-01-31 12:18:12 +00:00
####################################################################################
library & projects: Update Makefiles Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-18 13:15:22 +00:00
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
cn0561_coraz7s: Initial commit Because the inferface signals which pass through the eval board's Arduino connector are connected to level shifters the design will not work at the maximum clk frequency of 48MHz. The maximum tested frequency is 24MHz.
2022-01-31 12:18:12 +00:00
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := cn0561_coraz7s
M_DEPS += ../common/cn0561_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v
Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-23 12:10:43 +00:00
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
cn0561_coraz7s: Initial commit Because the inferface signals which pass through the eval board's Arduino connector are connected to level shifters the design will not work at the maximum clk frequency of 48MHz. The maximum tested frequency is 24MHz.
2022-01-31 12:18:12 +00:00
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk