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pluto_hdl_adi/projects/common/a10soc/system_project.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
projects/common: Add system_top _project templates Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct code and modify according to guidelines * Added spacing to ports declaration * Corrected coding mistakes/misspelling * Modified/added variables names * Added seetings (intel) and removed specific optimization settings * Added assignments to unassigned pins (gpios) Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct/Add missing wrapper ports and iobufs * Added port in wrapper (mainly spi) according to base design file * Added instances of iobufs where missing * Corrected gpio assignments or added missing ones * Corrected minor guidelines mistakes Signed-off-by: laurent-19 <laurentiu.popa@analog.com> ac701/system_top.v: Change top based on previous projects * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> projects/common: Modify templates to build without errors * Changed path for adi_env.tcl * Moved adi_project command before assign intel * Removed unnecessary spi signals * Added spi ports with default logic * a10soc: Removed pl-ddr signals and ports * ac701: system_bd: Modified mdio interface system_project: Added adi_board, adiobuf sourcing system_top: Removed hdmi, i2c, fanpwm, spdif ports according to base design * c5soc: Added version settings Removed unused gpios * microzed: system_bd: Enabled RTS1 to use FCLK system_top: Removed hdmi, i2c, unused gpios * vc709: Separated input from ouput gpio, according to bd Removed unnecessary ports Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Delete microzed vmk_es templates * Removed hp0 interconnect from cora base design * Added extra line to files de10nano Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-06-23 14:52:51 +00:00
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_project_intel.tcl
adi_project template_a10soc
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
execute_flow -compile