2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2023-04-06 06:24:19 +00:00
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2023-07-06 12:08:22 +00:00
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# create board design
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2023-04-06 06:24:19 +00:00
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# set Kria SOM240_1 connector to KV260 evaluation carrier
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set_property board_connections {som240_1_connector xilinx.com:kv260_carrier:som240_1_connector:1.3} [current_project]
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# default ports
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# default ports
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create_bd_port -dir O -from 2 -to 0 spi0_csn
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create_bd_port -dir O spi0_sclk
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create_bd_port -dir O spi0_mosi
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create_bd_port -dir I spi0_miso
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create_bd_port -dir I -from 94 -to 0 gpio_i
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create_bd_port -dir O -from 94 -to 0 gpio_o
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create_bd_port -dir O -from 94 -to 0 gpio_t
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# instance: sys_ps8
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ad_ip_instance zynq_ultra_ps_e sys_ps8
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apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e \
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-config {apply_board_preset 1} [get_bd_cells sys_ps8]
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set_property -dict "CONFIG.PSU__PSS_REF_CLK__FREQMHZ 33.333333333 CONFIG.PSU__DDRC__CWL 16" [get_bd_cells sys_ps8]
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
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set_property -dict [list \
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CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
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CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
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CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
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CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
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CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
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] [get_bd_cells sys_ps8]
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# processor system reset instances for all the three system clocks
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_250m_rstgen
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ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_500m_rstgen
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ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps8/pl_clk0
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ad_connect sys_250m_clk sys_ps8/pl_clk1
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ad_connect sys_500m_clk sys_ps8/pl_clk2
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ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_ps8/pl_resetn0 sys_250m_rstgen/ext_reset_in
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ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
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ad_connect sys_ps8/pl_resetn0 sys_500m_rstgen/ext_reset_in
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ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
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ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
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ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
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ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
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# generic system clocks&resets pointers
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set sys_cpu_clk [get_bd_nets sys_cpu_clk]
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set sys_dma_clk [get_bd_nets sys_250m_clk]
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set sys_iodelay_clk [get_bd_nets sys_500m_clk]
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set sys_cpu_reset [get_bd_nets sys_cpu_reset]
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set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
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set sys_dma_reset [get_bd_nets sys_250m_reset]
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set sys_dma_resetn [get_bd_nets sys_250m_resetn]
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set sys_iodelay_reset [get_bd_nets sys_500m_reset]
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set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
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# gpio
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ad_connect gpio_i sys_ps8/emio_gpio_i
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ad_connect gpio_o sys_ps8/emio_gpio_o
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ad_connect gpio_t sys_ps8/emio_gpio_t
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# spi
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ad_ip_instance xlconcat spi0_csn_concat
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ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
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ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
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ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
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ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
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ad_connect spi0_csn_concat/dout spi0_csn
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ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
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ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
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ad_connect sys_ps8/emio_spi0_m_i spi0_miso
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ad_connect sys_ps8/emio_spi0_ss_i_n VCC
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ad_connect sys_ps8/emio_spi0_sclk_i GND
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ad_connect sys_ps8/emio_spi0_s_i GND
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ad_ip_instance xlconcat sys_concat_intc_0
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ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
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ad_ip_instance xlconcat sys_concat_intc_1
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ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
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ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
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ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
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ad_connect sys_concat_intc_1/In7 GND
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ad_connect sys_concat_intc_1/In6 GND
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ad_connect sys_concat_intc_1/In5 GND
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ad_connect sys_concat_intc_1/In4 GND
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ad_connect sys_concat_intc_1/In3 GND
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ad_connect sys_concat_intc_1/In2 GND
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ad_connect sys_concat_intc_1/In1 GND
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ad_connect sys_concat_intc_1/In0 GND
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ad_connect sys_concat_intc_0/In7 GND
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ad_connect sys_concat_intc_0/In6 GND
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ad_connect sys_concat_intc_0/In5 GND
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ad_connect sys_concat_intc_0/In4 GND
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ad_connect sys_concat_intc_0/In3 GND
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ad_connect sys_concat_intc_0/In2 GND
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ad_connect sys_concat_intc_0/In1 GND
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ad_connect sys_concat_intc_0/In0 GND
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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ad_connect sys_cpu_clk rom_sys_0/clk
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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