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pluto_hdl_adi/projects/dac_fmc_ebz/a10soc/system_qsys.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
dac_fmc_ebz: Add initial Arria10 SoC support Add support for the Arria 10 SoC development kit to the dac_fmc_ebz project. This allows to use the following FMC boards on the Arria 10 SoC development Kit carrier: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the board in its default configuration is not fully compatible with the mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is required. The rework concerns the LA01 and LA05 pins, which by default are not connected to the FPGA. The changes required are: LA01_P_CC R612: R0 -> DNI R610: DNI -> R0 LA01_N_CC R613: R0 -> DNI R611: DNI -> R0 LA05_P R621: R0 -> DNI R620: DNI -> R0 LA05_N R633: R0 -> DNI R632: DNI -> R0 The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this all 4 possible txen signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * A10SoC: 14.2 Gbps
2018-03-20 13:43:36 +00:00
set dac_fifo_address_width 13
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
dac_fmc_ebz: Add initial Arria10 SoC support Add support for the Arria 10 SoC development kit to the dac_fmc_ebz project. This allows to use the following FMC boards on the Arria 10 SoC development Kit carrier: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the board in its default configuration is not fully compatible with the mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is required. The rework concerns the LA01 and LA05 pins, which by default are not connected to the FPGA. The changes required are: LA01_P_CC R612: R0 -> DNI R610: DNI -> R0 LA01_N_CC R613: R0 -> DNI R611: DNI -> R0 LA05_P R621: R0 -> DNI R620: DNI -> R0 LA05_N R633: R0 -> DNI R632: DNI -> R0 The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this all 4 possible txen signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * A10SoC: 14.2 Gbps
2018-03-20 13:43:36 +00:00
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
if [info exists ad_project_dir] {
source ../../common/dac_fmc_ebz_qsys.tcl
} else {
source ../common/dac_fmc_ebz_qsys.tcl
}
sysid_intel: Added sysid to intel projects
2020-08-18 20:52:39 +00:00
#system ID
set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file;
sysid_intel: Added sysid to intel projects
2020-08-18 20:52:39 +00:00