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pluto_hdl_adi/projects/dac_fmc_ebz/zc706/system_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P MGTREFCLK0P_109_AD10
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N MGTREFCLK0N_109_AD9
dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
2022-02-04 13:45:28 +00:00
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[7]] ; ## C02 FMC_HPC_DP0_C2M_P MGTXTXP0_109_AK10
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[7]] ; ## C03 FMC_HPC_DP0_C2M_N MGTXTXN0_109_AK9
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[6]] ; ## A22 FMC_HPC_DP1_C2M_P MGTXTXP1_109_AK6
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[6]] ; ## A23 FMC_HPC_DP1_C2M_N MGTXTXN1_109_AK5
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[5]] ; ## A26 FMC_HPC_DP2_C2M_P MGTXTXP2_109_AJ4
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[5]] ; ## A27 FMC_HPC_DP2_C2M_N MGTXTXN2_109_AJ3
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[4]] ; ## A30 FMC_HPC_DP3_C2M_P MGTXTXP3_109_AK2
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[4]] ; ## A31 FMC_HPC_DP3_C2M_N MGTXTXN3_109_AK1
set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[2]] ; ## A34 FMC_HPC_DP4_C2M_P MGTXTXP0_110_AH2
set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[2]] ; ## A35 FMC_HPC_DP4_C2M_N MGTXTXN0_110_AH1
set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[0]] ; ## A38 FMC_HPC_DP5_C2M_P MGTXTXP1_110_AF2
set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[0]] ; ## A39 FMC_HPC_DP5_C2M_N MGTXTXN1_110_AF1
set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[1]] ; ## B36 FMC_HPC_DP6_C2M_P MGTXTXP2_110_AE4
set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[1]] ; ## B37 FMC_HPC_DP6_C2M_N MGTXTXN2_110_AE3
set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[3]] ; ## B32 FMC_HPC_DP7_C2M_P MGTXTXP3_110_AD2
set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[3]] ; ## B33 FMC_HPC_DP7_C2M_N MGTXTXN3_110_AD1
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p[0]] ; ## D07 FMC_HPC_LA01_P IO_L13P_T2_MRCC_11_AG21
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n[0]] ; ## D08 FMC_HPC_LA01_N IO_L13N_T2_MRCC_11_AH21
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p[1]] ; ## H07 FMC_HPC_LA02_P IO_L16P_T2_11_AK17
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n[1]] ; ## H08 FMC_HPC_LA02_N IO_L16N_T2_11_AK18
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## G06 FMC_HPC_LA00_P IO_L14P_T2_SRCC_11_AF20
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## G07 FMC_HPC_LA00_N IO_L14N_T2_SRCC_11_AG20
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_en] ; ## D12 FMC_HPC_LA05_N IO_L5N_T0_11_AH24
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G09 FMC_HPC_LA03_P IO_L17P_T2_11_AH19
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G10 FMC_HPC_LA03_N IO_L17N_T2_11_AJ19
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## H10 FMC_HPC_LA04_P IO_L15P_T2_DQS_11_AJ20
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## H11 FMC_HPC_LA04_N IO_L15N_T2_DQS_11_AK20
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P IO_L5P_T0_11_AH23
# For AD916(1,2,3,4)-FMC-EBZ
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk2] ; ## D14 FMC_HPC_LA09_P IO_L10P_T1_11
# For AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ, AD9152-FMC-EBZ, AD9154-FMC-EBZ
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports dac_ctrl[0]] ; ## H13 FMC_HPC_LA07_P IO_L4P_T0_11_AJ23
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports dac_ctrl[3]] ; ## H14 FMC_HPC_LA07_N IO_L4N_T0_11_AJ24
# For AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports dac_ctrl[1]] ; ## C10 FMC_HPC_LA06_P IO_L6P_T0_11_AG22
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports dac_ctrl[2]] ; ## C11 FMC_HPC_LA06_N IO_L6P_T0_11_AG22
# For AD916(1,2,3,4)-FMC-EBZ
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports dac_ctrl[4]] ; ## D15 FMC_HPC_LA09_P IO_L10N_T1_11
# PMOD 1 header
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25} [get_ports pmod_spi_clk] ; ## PMOD1_0_LS IO_L3P_T0_DQS_11_AJ21
set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS25} [get_ports pmod_spi_csn] ; ## PMOD1_1_LS IO_L3N_T0_DQS_11_AK21
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports pmod_spi_mosi] ; ## PMOD1_2_LS IO_L19P_T3_11_AB21
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports pmod_spi_miso] ; ## PMOD1_3_LS IO_L24N_T3_10_AB16
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports pmod_gpio[0]] ; ## PMOD1_4_LS IO_L6P_T0_9_Y20
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports pmod_gpio[1]] ; ## PMOD1_5_LS IO_L6N_T0_VREF_9_AA20
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pmod_gpio[2]] ; ## PMOD1_6_LS IO_L11P_T1_SRCC_9_AC18
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pmod_gpio[3]] ; ## PMOD1_7_LS IO_L11N_T1_SRCC_9_AC19
# clocks
# Maximum lane of 10.3125 (Maximum supported by the ZC706)
create_clock -name tx_ref_clk -period 3.879 [get_ports tx_ref_clk_p]
create_clock -name tx_div_clk -period 3.879 [get_pins i_system_wrapper/system_i/util_dac_jesd204_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Center-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_ref_clk] \
[expr [get_property PERIOD [get_clocks tx_ref_clk]] / 2] \
[get_ports {tx_sysref_*}]