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pluto_hdl_adi/projects/daq2/zcu102/system_project.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../../scripts/adi_env.tcl
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2018-08-14 08:43:32 +00:00
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
daq2/zcu102- kcu105 copy
2016-09-30 14:50:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_board.tcl
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
# Parameter description:
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
adi_project daq2_zcu102 0 [list \
RX_JESD_M [get_env_param RX_JESD_M 2 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 2 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
]
daq2/zcu102- 2016.2 updates
2016-09-30 15:54:15 +00:00
adi_project_files daq2_zcu102 [list \
daq2/zcu102- kcu105 copy
2016-09-30 14:50:10 +00:00
"../common/daq2_spi.v" \
"system_top.v" \
"system_constr.xdc"\
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
"$ad_hdl_dir/library/common/ad_iobuf.v" \
daq2/zcu102- 2016.2 updates
2016-09-30 15:54:15 +00:00
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
daq2/zcu102- kcu105 copy
2016-09-30 14:50:10 +00:00
daq2/zcu102- 2016.2 updates
2016-09-30 15:54:15 +00:00
adi_project_run daq2_zcu102
daq2/zcu102- kcu105 copy
2016-09-30 14:50:10 +00:00
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
## To improve timing in the axi_ad9680_offload component
set_property strategy Performance_Retiming [get_runs impl_1]