2023-07-10 08:38:46 +00:00
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###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2014-12-08 15:44:15 +00:00
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# ad9625
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set_property -dict {PACKAGE_PIN A10 } [get_ports rx_ref_clk_0_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_0_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N
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set_property -dict {PACKAGE_PIN G6 } [get_ports rx_data_0_p[0]] ; ## A18 FMC1_HPC_DP5_M2C_P
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set_property -dict {PACKAGE_PIN G5 } [get_ports rx_data_0_n[0]] ; ## A19 FMC1_HPC_DP5_M2C_N
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set_property -dict {PACKAGE_PIN F8 } [get_ports rx_data_0_p[1]] ; ## B16 FMC1_HPC_DP6_M2C_P
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set_property -dict {PACKAGE_PIN F7 } [get_ports rx_data_0_n[1]] ; ## B17 FMC1_HPC_DP6_M2C_N
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set_property -dict {PACKAGE_PIN H8 } [get_ports rx_data_0_p[2]] ; ## A14 FMC1_HPC_DP4_M2C_P
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set_property -dict {PACKAGE_PIN H7 } [get_ports rx_data_0_n[2]] ; ## A15 FMC1_HPC_DP4_M2C_N
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set_property -dict {PACKAGE_PIN E6 } [get_ports rx_data_0_p[3]] ; ## B12 FMC1_HPC_DP7_M2C_P
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set_property -dict {PACKAGE_PIN E5 } [get_ports rx_data_0_n[3]] ; ## B13 FMC1_HPC_DP7_M2C_N
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set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_0_p[4]] ; ## A10 FMC1_HPC_DP3_M2C_P
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set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_0_n[4]] ; ## A11 FMC1_HPC_DP3_M2C_N
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set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_0_p[5]] ; ## A06 FMC1_HPC_DP2_M2C_P
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set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_0_n[5]] ; ## A07 FMC1_HPC_DP2_M2C_N
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set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_0_p[6]] ; ## C06 FMC1_HPC_DP0_M2C_P
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set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_0_n[6]] ; ## C07 FMC1_HPC_DP0_M2C_N
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set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_0_p[7]] ; ## A02 FMC1_HPC_DP1_M2C_P
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set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_0_n[7]] ; ## A03 FMC1_HPC_DP1_M2C_N
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set_property -dict {PACKAGE_PIN K8 } [get_ports rx_ref_clk_1_p] ; ## D04 FMC2_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN K7 } [get_ports rx_ref_clk_1_n] ; ## D05 FMC2_HPC_GBTCLK0_M2C_N
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2019-06-05 13:37:34 +00:00
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set_property -dict {PACKAGE_PIN V4 } [get_ports rx_data_1_p[0]] ; ## A18 FMC2_HPC_DP5_M2C_P
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set_property -dict {PACKAGE_PIN V3 } [get_ports rx_data_1_n[0]] ; ## A19 FMC2_HPC_DP5_M2C_N
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set_property -dict {PACKAGE_PIN U6 } [get_ports rx_data_1_p[1]] ; ## B16 FMC2_HPC_DP6_M2C_P
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set_property -dict {PACKAGE_PIN U5 } [get_ports rx_data_1_n[1]] ; ## B17 FMC2_HPC_DP6_M2C_N
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set_property -dict {PACKAGE_PIN W6 } [get_ports rx_data_1_p[2]] ; ## A14 FMC2_HPC_DP4_M2C_P
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set_property -dict {PACKAGE_PIN W5 } [get_ports rx_data_1_n[2]] ; ## A15 FMC2_HPC_DP4_M2C_N
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set_property -dict {PACKAGE_PIN R6 } [get_ports rx_data_1_p[3]] ; ## B12 FMC2_HPC_DP7_M2C_P
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set_property -dict {PACKAGE_PIN R5 } [get_ports rx_data_1_n[3]] ; ## B13 FMC2_HPC_DP7_M2C_N
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set_property -dict {PACKAGE_PIN J6 } [get_ports rx_data_1_p[4]] ; ## A10 FMC2_HPC_DP3_M2C_P
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set_property -dict {PACKAGE_PIN J5 } [get_ports rx_data_1_n[4]] ; ## A11 FMC2_HPC_DP3_M2C_N
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set_property -dict {PACKAGE_PIN L6 } [get_ports rx_data_1_p[5]] ; ## A06 FMC2_HPC_DP2_M2C_P
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set_property -dict {PACKAGE_PIN L5 } [get_ports rx_data_1_n[5]] ; ## A07 FMC2_HPC_DP2_M2C_N
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set_property -dict {PACKAGE_PIN P8 } [get_ports rx_data_1_p[6]] ; ## C06 FMC2_HPC_DP0_M2C_P
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set_property -dict {PACKAGE_PIN P7 } [get_ports rx_data_1_n[6]] ; ## C07 FMC2_HPC_DP0_M2C_N
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set_property -dict {PACKAGE_PIN N6 } [get_ports rx_data_1_p[7]] ; ## A02 FMC2_HPC_DP1_M2C_P
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set_property -dict {PACKAGE_PIN N5 } [get_ports rx_data_1_n[7]] ; ## A03 FMC2_HPC_DP1_M2C_N
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2014-12-08 15:44:15 +00:00
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2019-06-05 13:37:34 +00:00
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set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS} [get_ports rx_sysref_p] ; ## G06 FMC1_HPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS} [get_ports rx_sysref_n] ; ## G07 FMC1_HPC_LA00_CC_N
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2014-12-08 15:44:15 +00:00
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set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_0_p] ; ## D08 FMC1_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_0_n] ; ## D09 FMC1_HPC_LA01_CC_N
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2019-06-05 13:37:34 +00:00
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set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS} [get_ports rx_sync_1_p] ; ## H07 FMC1_HPC_LA02_P
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set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS} [get_ports rx_sync_1_n] ; ## H08 FMC1_HPC_LA02_N
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2014-12-08 15:44:15 +00:00
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set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_0] ; ## D11 FMC1_HPC_LA05_P
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set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn_1] ; ## D12 FMC1_HPC_LA05_N
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set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## C14 FMC1_HPC_LA10_P
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set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## C15 FMC1_HPC_LA10_N
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set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVCMOS18} [get_ports spi_dirn] ; ## H19 FMC1_HPC_LA15_P
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set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports pwdn_0] ; ## H13 FMC1_HPC_LA07_P
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set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports rst_0] ; ## C10 FMC1_HPC_LA06_P
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set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports drst_0] ; ## G12 FMC1_HPC_LA08_P
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set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports arst_0] ; ## D14 FMC1_HPC_LA09_P
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set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports fd_0] ; ## H10 FMC1_HPC_LA04_P
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set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports irq_0] ; ## G09 FMC1_HPC_LA03_P
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set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports pwdn_1] ; ## H14 FMC1_HPC_LA07_N
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set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports rst_1] ; ## C11 FMC1_HPC_LA06_N
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set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports drst_1] ; ## G13 FMC1_HPC_LA08_N
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set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports arst_1] ; ## D15 FMC1_HPC_LA09_N
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set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports fd_1] ; ## H11 FMC1_HPC_LA04_N
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set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports irq_1] ; ## G10 FMC1_HPC_LA03_N
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set_property -dict {PACKAGE_PIN L37 IOSTANDARD LVCMOS18} [get_ports pwr_good] ; ## H20 FMC1_HPC_LA15_N
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set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H16 FMC1_HPC_LA11_P
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set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H17 FMC1_HPC_LA11_N
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set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVDS} [get_ports vdither_p] ; ## G18 FMC1_HPC_LA16_P
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set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVDS} [get_ports vdither_n] ; ## G19 FMC1_HPC_LA16_N
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set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports dac_clk] ; ## D17 FMC1_HPC_LA13_P
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set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports dac_data] ; ## D18 FMC1_HPC_LA13_N
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set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports dac_sync_0] ; ## C18 FMC1_HPC_LA14_P
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set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVCMOS18} [get_ports dac_sync_1] ; ## C19 FMC1_HPC_LA14_N
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2015-10-15 14:45:46 +00:00
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set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports psync_0] ; ## G15 FMC1_HPC_LA12_P
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set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports psync_1] ; ## G16 FMC1_HPC_LA12_N
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2014-12-08 15:44:15 +00:00
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# clocks
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create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p]
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create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p]
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2016-11-23 21:21:57 +00:00
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create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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2014-12-08 15:44:15 +00:00
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2017-04-27 17:25:41 +00:00
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set_property IOB false [get_cells -hierarchical -filter {name =~ *SCK_O_NE_4_FDRE_INST}]
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