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pluto_hdl_adi/projects/pulsar_adc/common/pulsar_adc_bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
spi_engine: Create interface_ip.tcl (#1251) Use tcl script instead of static xmls for the interface. Easier to maintain and are not gitignored. Rename spi_master to spi_engine because every interface should be prefixed by the IP name; in this case, spi_engine. Also, remove interface/*.sv files on make clean and git ignore them. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 13:31:46 +00:00
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
### SPDX short identifier: ADIBSD
###############################################################################
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
spi_engine: Create interface_ip.tcl (#1251) Use tcl script instead of static xmls for the interface. Easier to maintain and are not gitignored. Rename spi_master to spi_engine because every interface should be prefixed by the IP name; in this case, spi_engine. Also, remove interface/*.sv files on make clean and git ignore them. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 13:31:46 +00:00
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 pulsar_adc_spi
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
pulsar_adc_pmdz: Port to ZedBoard Added support for AD40xx family in the PulSAR ADC project. --------- Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2024-04-24 12:43:57 +00:00
# If the ADC resolution <= 16, data_width is set 16 else 32
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
set data_width 32
set async_spi_clk 1
set num_cs 1
set num_sdi 1
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
set num_sdo 1
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
set sdi_delay 1
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
set echo_sclk 0
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
set hier_spi_engine spi_pulsar_adc
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
ad_ip_instance axi_clkgen spi_clkgen
ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
ad_ip_instance axi_pwm_gen pulsar_adc_trigger_gen
ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
# dma to receive data stream
ad_ip_instance axi_dmac axi_pulsar_adc_dma
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect spi_clk spi_clkgen/clk_0
ad_connect spi_clk pulsar_adc_trigger_gen/ext_clk
ad_connect $sys_cpu_clk pulsar_adc_trigger_gen/s_axi_aclk
ad_connect sys_cpu_resetn pulsar_adc_trigger_gen/s_axi_aresetn
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/trigger
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect axi_pulsar_adc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
ad_connect $hier_spi_engine/m_spi pulsar_adc_spi
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect $sys_cpu_clk $hier_spi_engine/clk
ad_connect spi_clk $hier_spi_engine/spi_clk
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect sys_cpu_resetn $hier_spi_engine/resetn
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
ad_connect sys_cpu_resetn axi_pulsar_adc_dma/m_dest_axi_aresetn
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
ad_cpu_interconnect 0x44a30000 axi_pulsar_adc_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen
ad_cpu_interconnect 0x44b00000 pulsar_adc_trigger_gen
ad_cpu_interrupt "ps-13" "mb-13" axi_pulsar_adc_dma/irq
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq
pulsar_adc_pmdz: Initial commit
2021-07-27 13:06:13 +00:00
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023)
2022-09-29 12:14:57 +00:00
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_pulsar_adc_dma/m_dest_axi