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pluto_hdl_adi/library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc

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adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Updated constraints
2015-04-30 11:23:24 +00:00
set_property ASYNC_REG TRUE \
[get_cells -hier *axi_waddr_m1_reg*] \
[get_cells -hier *axi_waddr_m2_reg*] \
axi_adcfifo_constr.xdc: Add missing backslash to command
2018-02-13 15:15:08 +00:00
[get_cells -hier *adc_xfer_req_m_reg[0]*] \
axi_adcfifo: Add missing constraints Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 09:31:07 +00:00
[get_cells -hier *axi_xfer_req_m_reg[0]*]
axi_adcfifo: Updated constraints
2015-04-30 11:23:24 +00:00
adcfifo: axi version
2015-04-07 20:16:17 +00:00
set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *up_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *up_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
axi_adcfifo: Add missing constraints Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 09:31:07 +00:00
set_false_path -from [get_cells *axi_waddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_waddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *dma_raddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_raddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Updated constraints
2015-04-30 11:23:24 +00:00
set_false_path \
-to [get_cells *adc_xfer_req_m_reg[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
axi_adcfifo: Add missing constraints Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 09:31:07 +00:00
set_false_path \
-to [get_cells *axi_xfer_req_m_reg[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]