zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/ad9467_fmc/common/ad9467_bd.tcl

86 lines
3.3 KiB
Tcl
Raw Normal View History

ad9467 : initial checkin
2014-04-09 14:34:40 +00:00
ad9467_zed: Update project to the new framework.
2015-04-01 11:38:39 +00:00
# ad9467
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_data_or_p
create_bd_port -dir I adc_data_or_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_n
create_bd_port -dir I -from 7 -to 0 adc_data_in_p
# adc peripheral
set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467]
set axi_ad9467_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9467_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9467_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9467_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9467_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma
ad9467_zed: Update project to the new framework.
2015-04-01 11:38:39 +00:00
# connections (ad9467)
ad_connect adc_clk_in_p axi_ad9467/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9467/adc_clk_in_n
ad_connect adc_data_in_n axi_ad9467/adc_data_in_n
ad_connect adc_data_in_p axi_ad9467/adc_data_in_p
ad_connect adc_data_or_p axi_ad9467/adc_or_in_p
ad_connect adc_data_or_n axi_ad9467/adc_or_in_n
ad_connect axi_ad9467/adc_clk axi_ad9467_dma/fifo_wr_clk
ad_connect sys_200m_clk axi_ad9467/delay_clk
ad_connect axi_ad9467/adc_valid axi_ad9467_dma/fifo_wr_en
ad_connect axi_ad9467/adc_data axi_ad9467_dma/fifo_wr_din
ad_connect axi_ad9467/adc_dovf axi_ad9467_dma/fifo_wr_overflow
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad9467
ad_cpu_interconnect 0x44A30000 axi_ad9467_dma
# memory inteconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9467_dma/m_dest_axi
ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma
2015-06-03 10:34:20 +00:00
ad_connect sys_cpu_resetn axi_ad9467_dma/m_dest_axi_aresetn
ad9467_zed: Update project to the new framework.
2015-04-01 11:38:39 +00:00
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad9467_dma/irq
# ila (with fifo to prevent timing failure)
set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 ila_fifo]
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
set_property -dict [list CONFIG.Input_Depth {128}] $ila_fifo
set_property -dict [list CONFIG.Output_Data_Width {32}] $ila_fifo
set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_fifo
set_property -dict [list CONFIG.Reset_Pin {false}] $ila_fifo
set ila_ad9467_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_ad9467_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9467_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ad9467_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_ad9467_mon
ad_connect sys_200m_clk ila_ad9467_mon/clk
ad_connect axi_ad9467/adc_clk ila_fifo/wr_clk
ad_connect sys_200m_clk ila_fifo/rd_clk
ad_connect ila_fifo/din axi_ad9467/adc_data
ad_connect ila_fifo/rd_en "VCC"
ad_connect ila_fifo/wr_en "VCC"
ad_connect ila_fifo/dout ila_ad9467_mon/probe0
ad9467 : initial checkin
2014-04-09 14:34:40 +00:00