378 lines
11 KiB
Coq
378 lines
11 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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module axi_hdmi_tx (
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// hdmi interface
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hdmi_clk,
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hdmi_out_clk,
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// 16-bit interface
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hdmi_16_hsync,
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hdmi_16_vsync,
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hdmi_16_data_e,
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hdmi_16_data,
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hdmi_16_es_data,
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// 24-bit interface
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hdmi_24_hsync,
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hdmi_24_vsync,
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hdmi_24_data_e,
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hdmi_24_data,
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// 36-bit interface
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hdmi_36_hsync,
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hdmi_36_vsync,
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hdmi_36_data_e,
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hdmi_36_data,
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// vdma interface
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m_axis_mm2s_clk,
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m_axis_mm2s_fsync,
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m_axis_mm2s_fsync_ret,
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m_axis_mm2s_tvalid,
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m_axis_mm2s_tdata,
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m_axis_mm2s_tkeep,
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m_axis_mm2s_tlast,
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m_axis_mm2s_tready,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready);
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// parameters
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parameter PCORE_ID = 0;
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parameter PCORE_Cr_Cb_N = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_EMBEDDED_SYNC = 0;
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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parameter C_BASEADDR = 32'hffffffff;
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parameter C_HIGHADDR = 32'h00000000;
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// hdmi interface
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input hdmi_clk;
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output hdmi_out_clk;
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// 16-bit interface
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output hdmi_16_hsync;
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output hdmi_16_vsync;
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output hdmi_16_data_e;
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output [15:0] hdmi_16_data;
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output [15:0] hdmi_16_es_data;
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// 24-bit interface
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output hdmi_24_hsync;
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output hdmi_24_vsync;
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output hdmi_24_data_e;
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output [23:0] hdmi_24_data;
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// 36-bit interface
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output hdmi_36_hsync;
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output hdmi_36_vsync;
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output hdmi_36_data_e;
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output [35:0] hdmi_36_data;
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// vdma interface
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input m_axis_mm2s_clk;
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output m_axis_mm2s_fsync;
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input m_axis_mm2s_fsync_ret;
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input m_axis_mm2s_tvalid;
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input [63:0] m_axis_mm2s_tdata;
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input [ 7:0] m_axis_mm2s_tkeep;
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input m_axis_mm2s_tlast;
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output m_axis_mm2s_tready;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// reset and clocks
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wire up_rstn;
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wire up_clk;
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wire hdmi_rst;
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wire vdma_clk;
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wire vdma_rst;
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// internal signals
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s;
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wire up_ack_s;
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wire hdmi_full_range_s;
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wire hdmi_csc_bypass_s;
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wire [ 1:0] hdmi_srcsel_s;
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wire [23:0] hdmi_const_rgb_s;
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wire [15:0] hdmi_hl_active_s;
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wire [15:0] hdmi_hl_width_s;
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wire [15:0] hdmi_hs_width_s;
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wire [15:0] hdmi_he_max_s;
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wire [15:0] hdmi_he_min_s;
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wire [15:0] hdmi_vf_active_s;
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wire [15:0] hdmi_vf_width_s;
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wire [15:0] hdmi_vs_width_s;
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wire [15:0] hdmi_ve_max_s;
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wire [15:0] hdmi_ve_min_s;
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wire hdmi_fs_toggle_s;
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wire [ 8:0] hdmi_raddr_g_s;
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wire hdmi_tpm_oos_s;
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wire hdmi_status_s;
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wire vdma_fs_s;
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wire vdma_fs_ret_s;
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wire vdma_valid_s;
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wire [63:0] vdma_data_s;
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wire vdma_ready_s;
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wire vdma_wr_s;
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wire [ 8:0] vdma_waddr_s;
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wire [47:0] vdma_wdata_s;
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wire vdma_fs_ret_toggle_s;
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wire [ 8:0] vdma_fs_waddr_s;
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// signal name changes
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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assign vdma_clk = m_axis_mm2s_clk;
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assign vdma_valid_s = m_axis_mm2s_tvalid;
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assign vdma_data_s = m_axis_mm2s_tdata;
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assign vdma_fs_ret_s = m_axis_mm2s_fsync_ret;
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assign m_axis_mm2s_fsync = vdma_fs_s;
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assign m_axis_mm2s_tready = vdma_ready_s;
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// axi interface
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up_axi #(
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.PCORE_BASEADDR (C_BASEADDR),
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.PCORE_HIGHADDR (C_HIGHADDR))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s),
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.up_ack (up_ack_s));
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// processor interface
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up_hdmi_tx i_up (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_full_range (hdmi_full_range_s),
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.hdmi_csc_bypass (hdmi_csc_bypass_s),
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.hdmi_srcsel (hdmi_srcsel_s),
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.hdmi_const_rgb (hdmi_const_rgb_s),
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.hdmi_hl_active (hdmi_hl_active_s),
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.hdmi_hl_width (hdmi_hl_width_s),
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.hdmi_hs_width (hdmi_hs_width_s),
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.hdmi_he_max (hdmi_he_max_s),
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.hdmi_he_min (hdmi_he_min_s),
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.hdmi_vf_active (hdmi_vf_active_s),
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.hdmi_vf_width (hdmi_vf_width_s),
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.hdmi_vs_width (hdmi_vs_width_s),
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.hdmi_ve_max (hdmi_ve_max_s),
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.hdmi_ve_min (hdmi_ve_min_s),
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.hdmi_status (hdmi_status_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_clk_ratio (32'd1),
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.vdma_clk (vdma_clk),
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.vdma_rst (vdma_rst),
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.vdma_ovf (vdma_ovf_s),
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.vdma_unf (vdma_unf_s),
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.vdma_tpm_oos (vdma_tpm_oos_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s),
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.up_ack (up_ack_s));
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// vdma interface
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axi_hdmi_tx_vdma i_vdma (
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.hdmi_fs_toggle (hdmi_fs_toggle_s),
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.hdmi_raddr_g (hdmi_raddr_g_s),
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.vdma_clk (vdma_clk),
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.vdma_rst (vdma_rst),
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.vdma_fs (vdma_fs_s),
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.vdma_fs_ret (vdma_fs_ret_s),
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.vdma_valid (vdma_valid_s),
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.vdma_data (vdma_data_s),
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.vdma_ready (vdma_ready_s),
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.vdma_wr (vdma_wr_s),
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.vdma_waddr (vdma_waddr_s),
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.vdma_wdata (vdma_wdata_s),
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.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
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.vdma_fs_waddr (vdma_fs_waddr_s),
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.vdma_tpm_oos (vdma_tpm_oos_s),
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.vdma_ovf (vdma_ovf_s),
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.vdma_unf (vdma_unf_s));
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// hdmi interface
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axi_hdmi_tx_core #(
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.Cr_Cb_N(PCORE_Cr_Cb_N),
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.EMBEDDED_SYNC(PCORE_EMBEDDED_SYNC))
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i_tx_core (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_16_hsync (hdmi_16_hsync),
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.hdmi_16_vsync (hdmi_16_vsync),
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.hdmi_16_data_e (hdmi_16_data_e),
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.hdmi_16_data (hdmi_16_data),
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.hdmi_16_es_data (hdmi_16_es_data),
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.hdmi_24_hsync (hdmi_24_hsync),
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.hdmi_24_vsync (hdmi_24_vsync),
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.hdmi_24_data_e (hdmi_24_data_e),
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.hdmi_24_data (hdmi_24_data),
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.hdmi_36_hsync (hdmi_36_hsync),
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.hdmi_36_vsync (hdmi_36_vsync),
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.hdmi_36_data_e (hdmi_36_data_e),
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.hdmi_36_data (hdmi_36_data),
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|
.hdmi_fs_toggle (hdmi_fs_toggle_s),
|
||
|
|
.hdmi_raddr_g (hdmi_raddr_g_s),
|
||
|
|
.hdmi_tpm_oos (hdmi_tpm_oos_s),
|
||
|
|
.hdmi_status (hdmi_status_s),
|
||
|
|
.vdma_clk (vdma_clk),
|
||
|
|
.vdma_wr (vdma_wr_s),
|
||
|
|
.vdma_waddr (vdma_waddr_s),
|
||
|
|
.vdma_wdata (vdma_wdata_s),
|
||
|
|
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
|
||
|
|
.vdma_fs_waddr (vdma_fs_waddr_s),
|
||
|
|
.hdmi_full_range (hdmi_full_range_s),
|
||
|
|
.hdmi_csc_bypass (hdmi_csc_bypass_s),
|
||
|
|
.hdmi_srcsel (hdmi_srcsel_s),
|
||
|
|
.hdmi_const_rgb (hdmi_const_rgb_s),
|
||
|
|
.hdmi_hl_active (hdmi_hl_active_s),
|
||
|
|
.hdmi_hl_width (hdmi_hl_width_s),
|
||
|
|
.hdmi_hs_width (hdmi_hs_width_s),
|
||
|
|
.hdmi_he_max (hdmi_he_max_s),
|
||
|
|
.hdmi_he_min (hdmi_he_min_s),
|
||
|
|
.hdmi_vf_active (hdmi_vf_active_s),
|
||
|
|
.hdmi_vf_width (hdmi_vf_width_s),
|
||
|
|
.hdmi_vs_width (hdmi_vs_width_s),
|
||
|
|
.hdmi_ve_max (hdmi_ve_max_s),
|
||
|
|
.hdmi_ve_min (hdmi_ve_min_s));
|
||
|
|
|
||
|
|
// hdmi output clock
|
||
|
|
|
||
|
|
ODDR #(.INIT(1'b0)) i_clk_oddr (
|
||
|
|
.R (1'b0),
|
||
|
|
.S (1'b0),
|
||
|
|
.CE (1'b1),
|
||
|
|
.D1 (1'b1),
|
||
|
|
.D2 (1'b0),
|
||
|
|
.C (hdmi_clk),
|
||
|
|
.Q (hdmi_out_clk));
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ***************************************************************************
|
||
|
|
// ***************************************************************************
|