pluto_hdl_adi/.gitignore

*.cache
*.data
*.xpr
*.log
*.bld
*.chk
*.cmd_log
*.cxt
*.gise
*.gyd
*.jed
*.lso
*.mfd
*.nga
*.ngc
*.ngd
*.ngr
*.pad
*.pnx
*.prj
*.rpt
*.stx
*.syr
*.tim
*.tspec
*.vm6
*.xst
*.html
*.xrpt
*.err
*_html
*.sld
*.txt
*.qsys
*.csv
xst
netgen
iseconfig
xlnx_auto*
_ngo
_xmsgs
component.xml
*.jou
xgui
*.runs
*.srcs
*.sdk
.Xil
*_INFO.txt
*_dump.txt
db
*.asm.rpt
*.done
*.eda.rpt
*.fit.*
*.map.*
*.sta.*
*.qsf
*.qpf
*.qws
*.sof
*.rbf
system_qsys_script.tcl
hc_output
hps_isw_handoff
hps_sdram_*.csv
incremental_db
system_bd/
reconfig_mif
*.sopcinfo
*.jdi
*.pin
*.os
*webtalk*
*.xml
*.hw
gui
.timestamp_altera
ignore cache 2014-04-26 01:58:15 +00:00			`*.cache`
added gitignore 2014-03-05 15:47:16 +00:00			`*.data`
			`*.xpr`
			`*.log`
Update .gitignore file 2016-03-11 10:04:46 +00:00			`*.bld`
			`*.chk`
			`*.cmd_log`
			`*.cxt`
			`*.gise`
			`*.gyd`
			`*.jed`
			`*.lso`
			`*.mfd`
			`*.nga`
			`*.ngc`
			`*.ngd`
			`*.ngr`
			`*.pad`
			`*.pnx`
			`*.prj`
			`*.rpt`
			`*.stx`
			`*.syr`
			`*.tim`
			`*.tspec`
			`*.vm6`
			`*.xst`
			`*.html`
			`*.xrpt`
			`*.err`
			`*_html`
Update .gitignore 2016-12-19 15:37:05 +00:00			`*.sld`
			`*.txt`
			`*.qsys`
			`*.csv`
Update .gitignore file 2016-03-11 10:04:46 +00:00			`xst`
			`netgen`
			`iseconfig`
			`xlnx_auto*`
			`_ngo`
			`_xmsgs`
added gitignore 2014-03-05 15:47:16 +00:00			`component.xml`
			`*.jou`
			`xgui`
			`*.runs`
			`*.srcs`
			`*.sdk`
			`.Xil`
a5soc: increase pipeline for qsys 2014-05-04 14:38:53 +00:00			`*_INFO.txt`
			`*_dump.txt`
			`db`
			`*.asm.rpt`
			`*.done`
			`*.eda.rpt`
			`.fit.`
			`.map.`
			`.sta.`
			`*.qsf`
			`*.qpf`
			`*.qws`
			`*.sof`
Add generated files for Intel projects to .gitignore The system_db folder is autogenerated and contains all the files that are generated by the Platform Designer tool. The extension for Intel binary bitstreams is rbf. Add both of those to the .gitignore since they should not be under version control and just end up as clutter in `git status` otherwise. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-08-08 09:21:05 +00:00			`*.rbf`
Update .gitignore 2016-12-19 15:37:05 +00:00			`system_qsys_script.tcl`
a5soc: increase pipeline for qsys 2014-05-04 14:38:53 +00:00			`hc_output`
			`hps_isw_handoff`
			`hps_sdram_*.csv`
			`incremental_db`
Add generated files for Intel projects to .gitignore The system_db folder is autogenerated and contains all the files that are generated by the Platform Designer tool. The extension for Intel binary bitstreams is rbf. Add both of those to the .gitignore since they should not be under version control and just end up as clutter in `git status` otherwise. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-08-08 09:21:05 +00:00			`system_bd/`
a5soc: increase pipeline for qsys 2014-05-04 14:38:53 +00:00			`reconfig_mif`
			`*.sopcinfo`
			`*.jdi`
			`*.pin`
gitignore: add non-project stuff 2015-05-01 17:17:14 +00:00			`*.os`
			`webtalk`
ignore xml files 2015-08-14 19:33:11 +00:00			`*.xml`
ignore *.hw 2015-08-25 18:24:21 +00:00			`*.hw`
ignore gui 2015-09-22 20:32:02 +00:00			`gui`
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-03-27 09:21:09 +00:00			`.timestamp_altera`
a5soc: increase pipeline for qsys 2014-05-04 14:38:53 +00:00