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pluto_hdl_adi/projects/fmcomms2/zed/system_constr.xdc

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Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
# constraints
fmcomms2: Cosmetic changes Get rid of unwanted whitespaces.
2014-10-10 15:25:17 +00:00
# ad9361
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
fmcomms2: Cosmetic changes Get rid of unwanted whitespaces.
2014-10-10 15:25:17 +00:00
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 10:54:01 +00:00
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
fmcomms2: Cosmetic changes Get rid of unwanted whitespaces.
2014-10-10 15:25:17 +00:00
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
fmcomms2: Add an additional SPI interface for up/down converter board Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 15:47:07 +00:00
# spi pmod JA1
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_tx] ; ## JA1
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 15:16:14 +00:00
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_rx] ; ## JA7
fmcomms2: Add an additional SPI interface for up/down converter board Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 15:47:07 +00:00
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_udc_sclk] ; ## JA4
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 15:16:14 +00:00
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_udc_data] ; ## JA2
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports gpio_muxout_tx] ; ## JA3
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_muxout_rx] ; ## JA9
fmcomms2: Add an additional SPI interface for up/down converter board Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 15:47:07 +00:00
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.
2014-03-18 13:27:42 +00:00
# clocks
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 20:08:28 +00:00
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]