2015-09-18 17:24:26 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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iic_scl,
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iic_sda,
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gpio_bd,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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enable,
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txnrx,
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gpio_clksel,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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fmc_prstn,
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fmc_clk0_p,
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fmc_clk0_n,
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fmc_clk1_p,
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fmc_clk1_n,
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fmc_la_p,
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fmc_la_n,
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pmod0,
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pmod1,
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fmc_gt_ref_clk_p,
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fmc_gt_ref_clk_n,
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fmc_gt_tx_p,
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fmc_gt_tx_n,
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fmc_gt_rx_p,
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fmc_gt_rx_n);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout iic_scl;
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inout iic_sda;
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inout [11:0] gpio_bd;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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output enable;
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output txnrx;
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inout gpio_clksel;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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input fmc_prstn;
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input fmc_clk0_p;
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input fmc_clk0_n;
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input fmc_clk1_p;
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input fmc_clk1_n;
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inout [33:0] fmc_la_p;
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inout [33:0] fmc_la_n;
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inout [ 7:0] pmod0;
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inout [ 7:0] pmod1;
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input fmc_gt_ref_clk_p;
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input fmc_gt_ref_clk_n;
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output fmc_gt_tx_p;
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output fmc_gt_tx_n;
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input fmc_gt_rx_p;
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input fmc_gt_rx_n;
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// internal signals
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wire fmc_clk0_s;
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wire fmc_clk0;
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wire [31:0] up_clk0_count;
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wire fmc_clk1_s;
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wire fmc_clk1;
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wire [31:0] up_clk1_count;
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wire fmc_gt_ref_clk;
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wire [31:0] gpio_0_0_i;
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wire [31:0] gpio_0_0_o;
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wire [31:0] gpio_0_0_t;
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wire [31:0] gpio_0_1_i;
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wire [31:0] gpio_0_1_o;
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wire [31:0] gpio_0_1_t;
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wire [31:0] gpio_1_0_i;
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wire [31:0] gpio_1_0_o;
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wire [31:0] gpio_1_0_t;
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wire [31:0] gpio_1_1_i;
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wire [31:0] gpio_1_1_o;
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wire [31:0] gpio_1_1_t;
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wire [31:0] gpio_3_1_o;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire up_clk;
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wire up_rst;
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wire up_rstn;
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wire up_pn_err_clr;
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wire up_pn_oos_clr;
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wire up_pn_err;
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wire up_pn_oos;
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// instantiations
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IBUFDS i_ibufds_clk0 (
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.I (fmc_clk0_p),
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.IB (fmc_clk0_n),
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.O (fmc_clk0_s));
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BUFG i_bufg_clk0 (
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.I (fmc_clk0_s),
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.O (fmc_clk0));
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up_clock_mon i_clk0_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_clk0_count),
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.d_rst (up_rst),
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.d_clk (fmc_clk0));
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IBUFDS i_ibufds_clk1 (
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.I (fmc_clk1_p),
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.IB (fmc_clk1_n),
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.O (fmc_clk1_s));
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BUFG i_bufg_clk1 (
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.I (fmc_clk1_s),
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.O (fmc_clk1));
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up_clock_mon i_clk1_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_clk1_count),
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.d_rst (up_rst),
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.d_clk (fmc_clk1));
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IBUFDS_GTE2 i_ibufds_ref_clk (
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.CEB (1'd0),
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.I (fmc_gt_ref_clk_p),
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.IB (fmc_gt_ref_clk_n),
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.O (fmc_gt_ref_clk),
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.ODIV2 ());
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assign gpio_0_1_i[31:10] = 'd0;
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assign gpio_1_1_i[31:10] = 'd0;
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assign up_pn_err_clr = gpio_3_1_o[1];
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assign up_pn_oos_clr = gpio_3_1_o[0];
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ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod0_fmc_p (
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.dio_t ({gpio_0_1_t[9:0], gpio_0_0_t[31:0]}),
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.dio_i ({gpio_0_1_o[9:0], gpio_0_0_o[31:0]}),
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.dio_o ({gpio_0_1_i[9:0], gpio_0_0_i[31:0]}),
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.dio_p ({ pmod1[3],
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pmod1[2],
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pmod1[1],
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pmod1[0],
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pmod0[3],
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pmod0[2],
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pmod0[1],
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pmod0[0],
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fmc_la_n[16:0],
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fmc_la_p[16:0]}));
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ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod1_fmc_n (
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.dio_t ({gpio_1_1_t[9:0], gpio_1_0_t[31:0]}),
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.dio_i ({gpio_1_1_o[9:0], gpio_1_0_o[31:0]}),
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.dio_o ({gpio_1_1_i[9:0], gpio_1_0_i[31:0]}),
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.dio_p ({ pmod1[7],
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pmod1[6],
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pmod1[5],
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pmod1[4],
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pmod0[7],
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pmod0[6],
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pmod0[5],
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pmod0[4],
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fmc_la_n[33:17],
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fmc_la_p[33:17]}));
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2015-09-23 13:15:40 +00:00
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t ({gpio_t[51], gpio_t[46:32]}),
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.dio_i ({gpio_o[51], gpio_o[46:32]}),
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.dio_o ({gpio_i[51], gpio_i[46:32]}),
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.dio_p ({ gpio_clksel, // 51:51
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2015-09-18 17:24:26 +00:00
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
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.dio_t (gpio_t[11:0]),
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.dio_i (gpio_o[11:0]),
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.dio_o (gpio_i[11:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.fmc_gt_ref_clk0 (fmc_gt_ref_clk),
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.fmc_gt_ref_clk1 (fmc_gt_ref_clk),
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.fmc_gt_rx_n (fmc_gt_rx_n),
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.fmc_gt_rx_p (fmc_gt_rx_p),
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.fmc_gt_tx_n (fmc_gt_tx_n),
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.fmc_gt_tx_p (fmc_gt_tx_p),
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.gpio_0_0_i (gpio_0_0_i),
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.gpio_0_0_o (gpio_0_0_o),
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.gpio_0_0_t (gpio_0_0_t),
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.gpio_0_1_i (gpio_0_1_i),
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.gpio_0_1_o (gpio_0_1_o),
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.gpio_0_1_t (gpio_0_1_t),
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.gpio_1_0_i (gpio_1_0_i),
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.gpio_1_0_o (gpio_1_0_o),
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.gpio_1_0_t (gpio_1_0_t),
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.gpio_1_1_i (gpio_1_1_i),
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.gpio_1_1_o (gpio_1_1_o),
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.gpio_1_1_t (gpio_1_1_t),
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.gpio_2_0_i (up_clk0_count),
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.gpio_2_0_o (),
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.gpio_2_0_t (),
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.gpio_2_1_i (up_clk1_count),
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.gpio_2_1_o (),
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.gpio_2_1_t (),
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.gpio_3_0_i ({31'd0, fmc_prstn}),
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.gpio_3_0_o (),
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.gpio_3_0_t (),
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.gpio_3_1_i ({30'd0, up_pn_err, up_pn_oos}),
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.gpio_3_1_o (gpio_3_1_o),
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.gpio_3_1_t (),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.otg_vbusoc (1'b0),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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2015-09-18 19:34:36 +00:00
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.ps_intr_15 (1'b0),
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2015-09-18 17:24:26 +00:00
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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2015-09-18 19:34:36 +00:00
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.tdd_sync_i (1'b0),
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.tdd_sync_o (),
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.tdd_sync_t (),
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2015-09-18 17:24:26 +00:00
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx),
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.up_clk (up_clk),
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.up_enable (gpio_o[47]),
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.up_pn_err (up_pn_err),
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.up_pn_err_clr (up_pn_err_clr),
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.up_pn_oos (up_pn_oos),
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.up_pn_oos_clr (up_pn_oos_clr),
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.up_rst (up_rst),
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.up_rstn (up_rstn),
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.up_txnrx (gpio_o[48]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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