18 lines
820 B
Plaintext
18 lines
820 B
Plaintext
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# Primary clock definitions
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create_clock -name refclk -period 4 [get_ports fpga_refclk_in_p]
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# device clock
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create_clock -name tx_device_clk -period 4 [get_ports clkin6_p]
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create_clock -name rx_device_clk -period 4 [get_ports clkin10_p]
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create_clock -name tx_div_clk -period 4 [get_pins i_system_wrapper/system_i/util_mxfe_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4 [get_pins i_system_wrapper/system_i/util_mxfe_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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# Constraint SYSREFs
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# Assumption is that REFCLK and SYSREF have similar propagation delay,
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# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
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set_input_delay -clock [get_clocks tx_device_clk] \
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[get_property PERIOD [get_clocks tx_device_clk]] \
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[get_ports {sysref2_*}]
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