2014-09-04 14:12:16 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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2015-07-27 13:05:26 +00:00
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//
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2014-09-04 14:12:16 +00:00
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// All rights reserved.
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2015-07-27 13:05:26 +00:00
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//
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2014-09-04 14:12:16 +00:00
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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2015-07-27 13:05:26 +00:00
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//
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2014-09-04 14:12:16 +00:00
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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2015-07-27 13:05:26 +00:00
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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2014-09-04 14:12:16 +00:00
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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2015-07-27 13:05:26 +00:00
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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2014-09-04 14:12:16 +00:00
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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2015-07-27 13:05:26 +00:00
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// fpga-fpga interface
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2014-09-04 14:12:16 +00:00
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2017-04-13 08:45:54 +00:00
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output eth_rx_clk,
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output eth_rx_cntrl,
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output [ 3:0] eth_rx_data,
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input eth_tx_clk,
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input eth_tx_cntrl,
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input [ 3:0] eth_tx_data,
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input eth_mdc,
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output eth_mdio_i,
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input eth_mdio_o,
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input eth_mdio_t,
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input eth_phy_resetn,
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2014-09-04 14:12:16 +00:00
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// phy interface
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2017-04-13 08:45:54 +00:00
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output phy_resetn,
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input phy_rx_clk,
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input phy_rx_cntrl,
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input [ 3:0] phy_rx_data,
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output phy_tx_clk_out,
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output phy_tx_cntrl,
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output [ 3:0] phy_tx_data,
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output phy_mdc,
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inout phy_mdio);
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2015-07-27 13:05:26 +00:00
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wire eth_rx_clk_90;
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wire eth_tx_clk_90;
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wire [ 4:0] eth_tx_data_h;
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wire [ 4:0] eth_tx_data_l;
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wire [ 4:0] phy_rx_data_h;
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wire [ 4:0] phy_rx_data_l;
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reg [ 4:0] eth_tx_data_h_d;
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reg [ 4:0] phy_rx_data_h_d;
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2016-12-13 08:30:24 +00:00
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reg [ 4:0] phy_rx_data_h_d1;
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reg [ 4:0] phy_rx_data_l_d;
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2015-07-27 13:05:26 +00:00
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// RX path
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altera_pll #(
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.fractional_vco_multiplier("false"),
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.reference_clock_frequency("125.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(1),
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.output_clock_frequency0("125.000000 MHz"),
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.phase_shift0("2000 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("0 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("0 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("0 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) eth_rx_pll_i (
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.rst (~eth_phy_resetn),
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.outclk (eth_rx_clk_90),
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.locked (),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (phy_rx_clk)
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);
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altddio_in #(
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.intended_device_family("Arria V"),
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.invert_input_clocks("OFF"),
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.lpm_hint("UNUSED"),
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.lpm_type("altddio_in"),
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.power_up_high("OFF"),
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.width(5)
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) eth_rx_path_in (
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.datain ({phy_rx_cntrl,phy_rx_data}),
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.inclock (phy_rx_clk),
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.dataout_h (phy_rx_data_h),
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.dataout_l (phy_rx_data_l),
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.aclr (~eth_phy_resetn),
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.aset (1'b0),
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.inclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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always @(posedge phy_rx_clk)
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begin
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phy_rx_data_h_d <= phy_rx_data_h;
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2016-12-13 08:30:24 +00:00
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phy_rx_data_h_d1 <= phy_rx_data_h_d;
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phy_rx_data_l_d <= phy_rx_data_l;
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2015-07-27 13:05:26 +00:00
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end
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altddio_out #(
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.extend_oe_disable("OFF"),
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.intended_device_family("Arria V"),
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.invert_output("OFF"),
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.lpm_hint("UNUSED"),
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.lpm_type("altddio_out"),
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.oe_reg("UNREGISTERED"),
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.power_up_high("OFF"),
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.width(5)
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) eth_rx_path_out (
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2016-12-13 08:30:24 +00:00
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.datain_h (phy_rx_data_h_d1),
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.datain_l (phy_rx_data_l_d),
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2015-07-27 13:05:26 +00:00
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.outclock (phy_rx_clk),
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.dataout ({eth_rx_cntrl,eth_rx_data}),
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.aclr (~eth_phy_resetn),
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.aset (1'b0),
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.oe (1'b1),
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.oe_out (),
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.outclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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2014-09-04 14:12:16 +00:00
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2015-07-27 13:05:26 +00:00
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altddio_out #(.width(1)) i_eth_rx_clk (
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.aset (1'b0),
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.sset (1'b0),
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.sclr (1'b0),
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.oe (1'b1),
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.oe_out (),
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.datain_h (1'b1),
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.datain_l (1'b0),
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.outclocken (1'b1),
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.aclr (1'b0),
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.outclock (eth_rx_clk_90),
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.dataout (eth_rx_clk));
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2014-09-04 14:12:16 +00:00
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2015-07-27 13:05:26 +00:00
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// assign eth_rx_clk = eth_rx_clk_90;
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// TX path
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altera_pll #(
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.fractional_vco_multiplier("false"),
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.reference_clock_frequency("125.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(1),
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.output_clock_frequency0("125.000000 MHz"),
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.phase_shift0("2000 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("0 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("0 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("0 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) eth_tx_pll_i (
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.rst (~eth_phy_resetn),
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.outclk (eth_tx_clk_90),
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.locked (),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (eth_tx_clk)
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);
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altddio_in #(
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.intended_device_family("Arria V"),
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.invert_input_clocks("OFF"),
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.lpm_hint("UNUSED"),
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.lpm_type("altddio_in"),
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.power_up_high("OFF"),
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.width(5))
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eth_tx_path_in (
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.datain({eth_tx_cntrl,eth_tx_data}),
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.inclock(eth_tx_clk_90),
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.dataout_h(eth_tx_data_h),
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.dataout_l(eth_tx_data_l));
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always @(posedge eth_tx_clk_90)
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begin
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eth_tx_data_h_d <= eth_tx_data_h;
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|
end
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|
|
|
|
|
|
|
altddio_out #(
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|
|
|
|
.extend_oe_disable("OFF"),
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|
|
|
|
.intended_device_family("Arria V"),
|
|
|
|
|
.invert_output("OFF"),
|
|
|
|
|
.lpm_hint("UNUSED"),
|
|
|
|
|
.lpm_type("altddio_out"),
|
|
|
|
|
.oe_reg("UNREGISTERED"),
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|
|
|
|
.power_up_high("OFF"),
|
|
|
|
|
.width(5)
|
|
|
|
|
) eth_tx_path_out (
|
|
|
|
|
.datain_h (eth_tx_data_h_d),
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|
|
|
|
.datain_l (eth_tx_data_l),
|
|
|
|
|
.outclock (eth_tx_clk_90),
|
|
|
|
|
.dataout ({phy_tx_cntrl,phy_tx_data}),
|
|
|
|
|
.aclr (~eth_phy_resetn),
|
|
|
|
|
.aset (1'b0),
|
|
|
|
|
.oe (1'b1),
|
|
|
|
|
.oe_out (),
|
|
|
|
|
.outclocken (1'b1),
|
|
|
|
|
.sclr (1'b0),
|
|
|
|
|
.sset (1'b0));
|
|
|
|
|
|
|
|
|
|
altddio_out #(.width(1)) i_phy_tx_clk_out (
|
|
|
|
|
.aset (1'b0),
|
|
|
|
|
.sset (1'b0),
|
|
|
|
|
.sclr (1'b0),
|
|
|
|
|
.oe (1'b1),
|
|
|
|
|
.oe_out (),
|
|
|
|
|
.datain_h (1'b1),
|
|
|
|
|
.datain_l (1'b0),
|
|
|
|
|
.outclocken (1'b1),
|
|
|
|
|
.aclr (1'b0),
|
|
|
|
|
.outclock (eth_tx_clk_90),
|
|
|
|
|
.dataout (phy_tx_clk_out));
|
|
|
|
|
|
|
|
|
|
// assign phy_tx_clk_out = eth_tx_clk_90;
|
|
|
|
|
|
|
|
|
|
// MDIO
|
2014-09-04 14:12:16 +00:00
|
|
|
|
|
|
|
|
assign phy_mdc = eth_mdc;
|
|
|
|
|
assign phy_mdio = (eth_mdio_t == 1'b0) ? eth_mdio_o : 1'bz;
|
|
|
|
|
assign eth_mdio_i = phy_mdio;
|
|
|
|
|
|
2015-07-27 13:05:26 +00:00
|
|
|
// Reset
|
|
|
|
|
|
|
|
|
|
assign phy_resetn = eth_phy_resetn ;
|
2014-09-04 14:12:16 +00:00
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
// ***************************************************************************
|
|
|
|
|
// ***************************************************************************
|
