pluto_hdl_adi/projects/daq3/a10gx/system_qsys.tcl


set dac_fifo_address_width 10

source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl
source ../common/daq3_qsys.tcl
daq3: A10GX, updated project to the TCL flow 2016-07-08 09:00:37 +00:00
daq3: A10GX, updated to the ADI JESD204 - changed lane rate to 12.33Gbps - added dac fifo 2017-10-25 13:41:26 +00:00			`set dac_fifo_address_width 10`

daq3: A10GX, updated project to the TCL flow 2016-07-08 09:00:37 +00:00			`source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl`
all: Rename altera to intel 2018-08-13 13:59:02 +00:00			`source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl`
daq3: A10GX, updated project to the TCL flow 2016-07-08 09:00:37 +00:00			`source ../common/daq3_qsys.tcl`