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pluto_hdl_adi/library/axi_clkgen/axi_clkgen_ip.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ip
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_create axi_clkgen
adi_ip_files axi_clkgen [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
lib_refactoring: Fix path of the IO macros
2016-08-05 15:00:34 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_clkgen.v" \
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
axi_clkgen: Infer CLKIN period Instead of having to manually specify the input clock period infer the values from the block design. This means that less configuration parameters need to be changed if the clock input frequency changes. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:20:26 +00:00
"bd/bd.tcl" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"axi_clkgen.v" ]
adi_ip_properties axi_clkgen
Remove library/scripts/common_bd.tcl Remove the script from the file list of the IPs that previously used it. axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-02 09:13:25 +00:00
adi_ip_bd axi_clkgen "bd/bd.tcl"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
library: Add link to wiki for IPs
2021-10-20 15:08:35 +00:00
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clkgen} [ipx::current_core]
axi_clkgen: Add interface definitions for clock inputs/outputs Add interface definition for the input and output clocks. This will allow the tools to recognize them as clocks and enable things like clock frequency propagation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:22:23 +00:00
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
axi_clkgen: Add enable parameters for secondary clock inputs/outputs The secondary clock inputs and outputs of the axi_clkgen are rarely used. Add enable parameters that need to be explicitly set before they are available. This allows to hide the secondary clock pins when they are not used in the block design. There are currently no projects which use the secondary clock inputs or outputs so there is no need to set these new parameters anywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:21:05 +00:00
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
axi_clkgen: Added a second input clock option
2015-11-06 15:55:29 +00:00
axi_clkgen: Add enable parameters for secondary clock inputs/outputs The secondary clock inputs and outputs of the axi_clkgen are rarely used. Add enable parameters that need to be explicitly set before they are available. This allows to hide the secondary clock pins when they are not used in the block design. There are currently no projects which use the secondary clock inputs or outputs so there is no need to set these new parameters anywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:21:05 +00:00
set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc]
set_property -dict {value_resolve_type user value_format bool value false} $param
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_clkgen: Add enable parameters for secondary clock inputs/outputs The secondary clock inputs and outputs of the axi_clkgen are rarely used. Add enable parameters that need to be explicitly set before they are available. This allows to hide the secondary clock pins when they are not used in the block design. There are currently no projects which use the secondary clock inputs or outputs so there is no need to set these new parameters anywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:21:05 +00:00
set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0]
set_property -dict [list \
display_name {Enable secondary clock input} \
widget {checkBox} \
] $param
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_clkgen: Add enable parameters for secondary clock inputs/outputs The secondary clock inputs and outputs of the axi_clkgen are rarely used. Add enable parameters that need to be explicitly set before they are available. This allows to hide the secondary clock pins when they are not used in the block design. There are currently no projects which use the secondary clock inputs or outputs so there is no need to set these new parameters anywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:21:05 +00:00
set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc]
set_property -dict {value_resolve_type user value_format bool value false} $param
set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0]
set_property -dict [list \
display_name {Enable secondary clock output} \
widget {checkBox} \
] $param
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
axi_clkgen: Add enable parameters for secondary clock inputs/outputs The secondary clock inputs and outputs of the axi_clkgen are rarely used. Add enable parameters that need to be explicitly set before they are available. This allows to hide the secondary clock pins when they are not used in the block design. There are currently no projects which use the secondary clock inputs or outputs so there is no need to set these new parameters anywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:21:05 +00:00
set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]
adi_set_ports_dependency clk2 ENABLE_CLKIN2 0
adi_set_ports_dependency clk_1 ENABLE_CLKOUT1
ipx::create_xgui_files $cc
ipx::save_core $cc