324 lines
9.7 KiB
Coq
324 lines
9.7 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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gpio_bd_i,
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gpio_bd_o,
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rx_clk_in_0_p,
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rx_clk_in_0_n,
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rx_frame_in_0_p,
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rx_frame_in_0_n,
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rx_data_in_0_p,
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rx_data_in_0_n,
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tx_clk_out_0_p,
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tx_clk_out_0_n,
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tx_frame_out_0_p,
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tx_frame_out_0_n,
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tx_data_out_0_p,
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tx_data_out_0_n,
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gpio_status_0,
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gpio_ctl_0,
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gpio_en_agc_0,
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mcs_sync,
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gpio_resetb_0,
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enable_0,
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txnrx_0,
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gpio_debug_1_0,
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gpio_debug_2_0,
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gpio_calsw_1_0,
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gpio_calsw_2_0,
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gpio_ad5355_rfen,
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gpio_ad5355_lock,
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rx_clk_in_1_p,
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rx_clk_in_1_n,
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rx_frame_in_1_p,
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rx_frame_in_1_n,
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rx_data_in_1_p,
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rx_data_in_1_n,
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tx_clk_out_1_p,
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tx_clk_out_1_n,
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tx_frame_out_1_p,
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tx_frame_out_1_n,
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tx_data_out_1_p,
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tx_data_out_1_n,
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gpio_status_1,
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gpio_ctl_1,
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gpio_en_agc_1,
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gpio_resetb_1,
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enable_1,
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txnrx_1,
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gpio_debug_3_1,
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gpio_debug_4_1,
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gpio_calsw_3_1,
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gpio_calsw_4_1,
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spi_ad9361_0,
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spi_ad9361_1,
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spi_ad5355,
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spi_clk,
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spi_mosi,
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spi_miso,
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ref_clk_p,
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ref_clk_n);
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input [12:0] gpio_bd_i;
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output [ 7:0] gpio_bd_o;
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input rx_clk_in_0_p;
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input rx_clk_in_0_n;
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input rx_frame_in_0_p;
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input rx_frame_in_0_n;
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input [ 5:0] rx_data_in_0_p;
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input [ 5:0] rx_data_in_0_n;
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output tx_clk_out_0_p;
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output tx_clk_out_0_n;
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output tx_frame_out_0_p;
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output tx_frame_out_0_n;
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output [ 5:0] tx_data_out_0_p;
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output [ 5:0] tx_data_out_0_n;
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input [ 7:0] gpio_status_0;
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output [ 3:0] gpio_ctl_0;
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output gpio_en_agc_0;
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output mcs_sync;
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output gpio_resetb_0;
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output enable_0;
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output txnrx_0;
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output gpio_debug_1_0;
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output gpio_debug_2_0;
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output gpio_calsw_1_0;
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output gpio_calsw_2_0;
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output gpio_ad5355_rfen;
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input gpio_ad5355_lock;
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input rx_clk_in_1_p;
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input rx_clk_in_1_n;
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input rx_frame_in_1_p;
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input rx_frame_in_1_n;
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input [ 5:0] rx_data_in_1_p;
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input [ 5:0] rx_data_in_1_n;
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output tx_clk_out_1_p;
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output tx_clk_out_1_n;
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output tx_frame_out_1_p;
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output tx_frame_out_1_n;
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output [ 5:0] tx_data_out_1_p;
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output [ 5:0] tx_data_out_1_n;
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input [ 7:0] gpio_status_1;
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output [ 3:0] gpio_ctl_1;
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output gpio_en_agc_1;
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output gpio_resetb_1;
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output enable_1;
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output txnrx_1;
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output gpio_debug_3_1;
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output gpio_debug_4_1;
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output gpio_calsw_3_1;
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output gpio_calsw_4_1;
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output spi_ad9361_0;
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output spi_ad9361_1;
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output spi_ad5355;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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input ref_clk_p;
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input ref_clk_n;
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// internal registers
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reg [ 2:0] mcs_sync_m = 'd0;
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reg mcs_sync = 'd0;
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// internal signals
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wire sys_100m_resetn;
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wire ref_clk_s;
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wire ref_clk;
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wire [ 94:0] gpio_i;
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wire [ 94:0] gpio_o;
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wire gpio_sync;
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wire gpio_open_44_44;
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wire gpio_open_15_15;
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wire [ 2:0] spi0_csn;
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wire spi0_clk;
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wire spi0_mosi;
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wire spi0_miso;
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wire [ 2:0] spi1_csn;
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wire spi1_clk;
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wire spi1_mosi;
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wire spi1_miso;
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wire txnrx_0;
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wire enable_0;
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wire txnrx_1;
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wire enable_1;
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// multi-chip synchronization
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always @(posedge ref_clk or negedge sys_100m_resetn) begin
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if (sys_100m_resetn == 1'b0) begin
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mcs_sync_m <= 3'd0;
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mcs_sync <= 1'd0;
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end else begin
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mcs_sync_m <= {mcs_sync_m[1:0], gpio_sync};
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mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1];
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end
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end
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// instantiations
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IBUFGDS i_ref_clk_ibuf (
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.I (ref_clk_p),
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.IB (ref_clk_n),
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.O (ref_clk_s));
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BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (ref_clk_s),
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.O (ref_clk));
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assign gpio_resetb_1 = gpio_o[65];
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assign gpio_i[64] = gpio_ad5355_lock;
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assign gpio_ad5355_rfen = gpio_o[63];
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assign gpio_calsw_4_1 = gpio_o[62];
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assign gpio_calsw_3_1 = gpio_o[61];
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assign gpio_calsw_2_0 = gpio_o[60];
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assign gpio_calsw_1_0 = gpio_o[59];
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assign gpio_txnrx_1 = gpio_o[58];
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assign gpio_enable_1 = gpio_o[57];
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assign gpio_en_agc_1 = gpio_o[56];
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assign gpio_txnrx_0 = gpio_o[55];
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assign gpio_enable_0 = gpio_o[54];
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assign gpio_en_agc_0 = gpio_o[53];
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assign gpio_resetb_0 = gpio_o[52];
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assign gpio_sync = gpio_o[51];
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assign gpio_open_44_44 = gpio_o[50];
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assign gpio_debug_4_0 = gpio_o[49];
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assign gpio_debug_3_0 = gpio_o[48];
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assign gpio_debug_2_0 = gpio_o[47];
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assign gpio_debug_1_0 = gpio_o[46];
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assign gpio_ctl_1 = gpio_o[45:42];
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assign gpio_ctl_0 = gpio_o[41:38];
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assign gpio_i[37:30] = gpio_status_1;
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assign gpio_i[29:22] = gpio_status_0;
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assign gpio_open_15_15 = gpio_o[21];
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assign gpio_bd_o = gpio_o[20:13];
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assign gpio_i[12: 0] = gpio_bd_i;
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assign gpio_i[94:65] = gpio_o[94:65];
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assign gpio_i[63:38] = gpio_o[63:38];
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assign gpio_i[21:14] = gpio_o[21:14];
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assign spi_ad9361_0 = spi0_csn[0];
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assign spi_ad9361_1 = spi0_csn[1];
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assign spi_ad5355 = spi0_csn[2];
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assign spi_clk = spi0_clk;
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assign spi_mosi = spi0_mosi;
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assign spi0_miso = spi_miso;
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assign spi1_miso = 1'b0;
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_14 (1'b0),
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.ps_intr_15 (1'b0),
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.rx_clk_in_0_n (rx_clk_in_0_n),
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.rx_clk_in_0_p (rx_clk_in_0_p),
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.rx_clk_in_1_n (rx_clk_in_1_n),
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.rx_clk_in_1_p (rx_clk_in_1_p),
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.rx_data_in_0_n (rx_data_in_0_n),
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.rx_data_in_0_p (rx_data_in_0_p),
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.rx_data_in_1_n (rx_data_in_1_n),
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.rx_data_in_1_p (rx_data_in_1_p),
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.rx_frame_in_0_n (rx_frame_in_0_n),
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.rx_frame_in_0_p (rx_frame_in_0_p),
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.rx_frame_in_1_n (rx_frame_in_1_n),
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.rx_frame_in_1_p (rx_frame_in_1_p),
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.spi0_csn (spi0_csn),
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.spi0_miso (spi0_miso),
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.spi0_mosi (spi0_mosi),
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.spi0_sclk (spi0_clk),
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.spi1_csn (spi1_csn),
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.spi1_miso (spi1_miso),
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.spi1_mosi (spi1_mosi),
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.spi1_sclk (spi1_clk),
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.sys_100m_resetn (sys_100m_resetn),
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.tx_clk_out_0_n (tx_clk_out_0_n),
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.tx_clk_out_0_p (tx_clk_out_0_p),
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.tx_clk_out_1_n (tx_clk_out_1_n),
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.tx_clk_out_1_p (tx_clk_out_1_p),
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.tx_data_out_0_n (tx_data_out_0_n),
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.tx_data_out_0_p (tx_data_out_0_p),
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.tx_data_out_1_n (tx_data_out_1_n),
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.tx_data_out_1_p (tx_data_out_1_p),
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.tx_frame_out_0_n (tx_frame_out_0_n),
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.tx_frame_out_0_p (tx_frame_out_0_p),
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.tx_frame_out_1_n (tx_frame_out_1_n),
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.tx_frame_out_1_p (tx_frame_out_1_p),
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.txnrx_0 (txnrx_0),
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.enable_0 (enable_0),
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.up_enable_0 (gpio_enable_0),
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.up_txnrx_0 (gpio_txnrx_0),
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.txnrx_1 (txnrx_1),
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.enable_1 (enable_1),
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.up_enable_1 (gpio_enable_1),
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.up_txnrx_1 (gpio_txnrx_1));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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