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pluto_hdl_adi/projects/adrv9371x/a10gx/system_constr.sdc

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adrv9371x: Initial commit -need to fix dc filter module for AD9371 / altera
2016-08-16 12:50:46 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
adrv9371x: altera: Convert to ADI JESD204 Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204 framework. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-22 20:26:57 +00:00
create_clock -period "8.138 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "8.138 ns" -name ref_clk1 [get_ports {ref_clk1}]
adrv9371x: Initial commit -need to fix dc filter module for AD9371 / altera
2016-08-16 12:50:46 +00:00
derive_pll_clocks
derive_clock_uncertainty
adrv9371x/a10gx- alt 16.1 updates
2017-06-07 13:19:03 +00:00
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
adrv9371x: Initial commit -need to fix dc filter module for AD9371 / altera
2016-08-16 12:50:46 +00:00
adrv9371x/a10gx: Add external flash support
2017-10-06 07:43:58 +00:00
set_false_path -from * -to [get_ports {flash_resetn}]