26 lines
743 B
Tcl
26 lines
743 B
Tcl
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package require -exact qsys 13.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_intel.tcl
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set_module_property NAME util_clkdiv
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set_module_property DESCRIPTION "Clock Division Utility"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_clkdiv
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_clkdiv
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add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE
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# defaults
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ad_alt_intf clock clk input 1
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ad_alt_intf reset reset input 1 if_clk
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ad_alt_intf clock clk_out output 1
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ad_alt_intf reset reset_out output 1 if_clk_out
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