97 lines
4.4 KiB
ReStructuredText
97 lines
4.4 KiB
ReStructuredText
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.. _spi_engine:
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SPI Engine
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================================================================================
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.. toctree::
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:hidden:
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Execution Module<spi_engine_execution>
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AXI Module<axi_spi_engine>
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Offload Module<spi_engine_offload>
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Interconnect Module<spi_engine_interconnect>
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Control Interface<control-interface>
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Offload Control Interface<offload-control-interface>
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SPI Bus Interface<spi-bus-interface>
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Instruction Set Specification<instruction-format>
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Tutorial - PulSAR ADC<tutorial>
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SPI Engine is a highly flexible and powerful SPI controller framework.
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It consist out of multiple sub-modules which communicate over well defined
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interfaces.
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This allows a high degree of flexibility and re-usability while at the same time
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staying highly customizable and easily extensible.
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The core component of the SPI Engine framework is a lean but powerful fully
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programmable execution module, which implements the SPI bus control logic.
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The SPI Engine execution module is controlled by a command stream which is
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generated by a separate module. Different command stream master modules are
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available and can be used depending on the system requirements.
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For example a software controlled memory mapped command stream offers high
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flexibility, while a offload core which executes a pre-programmed command stream
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when triggered by an external event allows for very low latency response times.
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By using a SPI Engine interconnect it is possible to connect multiple command
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stream master modules to a SPI Engine execution module.
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Sub-modules
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--------------------------------------------------------------------------------
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* :ref:`spi_engine execution`: Main module which processes a SPI engine command
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stream and implements the SPI bus interface logic.
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* :ref:`spi_engine axi`: Memory mapped software accessible interface to a
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SPI Engine command stream and/or offload cores.
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* :ref:`spi_engine offload`: Stores a SPI Engine command stream, execution is
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triggered by an external event.
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* :ref:`spi_engine interconnect`: Connects multiple SPI Engine command streams
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to a SPI Engine execution module.
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Interfaces
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--------------------------------------------------------------------------------
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* :ref:`spi_engine control-interface`: SPI Engine command stream.
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* :ref:`spi_engine offload-control-interface`: Program the command stream stored
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in a offload module.
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* :ref:`spi_engine spi-bus-interface`: Low-level SPI bus interface.
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Software
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* :dokuwiki:`Linux Driver:resources/tools-software/linux-drivers/spi/spi_engine`:
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Linux driver for the SPI Engine framework.
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* :ref:`spi_engine instruction-format`: Overview of the SPI Engine Instruction
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format.
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Related IP Cores
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--------------------------------------------------------------------------------
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This list contains cores that are not part of the core SPI engine framework but
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make use of its interfaces and are intend to be used together with the SPI engine
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framework.
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* :dokuwiki:`util-sigma-delta-spi:resources/fpga/peripherals/util_sigma_delta_spi`:
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Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family.
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Examples
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--------------------------------------------------------------------------------
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* :dokuwiki:`CN0363:resources/eval/user-guides/eval-cn0363-pmdz`:
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Colorimeter application using the :part:`AD7175-2` Sigma-Delta ADC.
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* :dokuwiki:`resources/eval/user-guides/adaq7980-sdz`:
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A 16-bit ADC subsystem with four common signal processing and conditioning blocks.
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* :dokuwiki:`resources/tools-software/uc-drivers/ad5766`:
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16-channel, 16-/12-bit, voltage output Digital-to-Analog Converters (DAC).
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* :dokuwiki:`CN0363:resources/eval/user-guides/eval-cn0363-pmdz`:
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The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC).
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* :git-hdl:`master:projects/ad40xx_fmc`
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Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs.
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* :dokuwiki:`AD469x:resources/eval/user-guides/ad469x`:
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16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC.
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* :dokuwiki:`AD4630-24 / AD4030-24 / AD4630-16:resources/eval/user-guides/ad463x/hdl`:
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16/24-Bit, 2 MSPS Single or Dual Channel SAR ADC.
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Additional Resources
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* :download:`Presentation: SPI Engine Design Philosophy <https://wiki.analog.com/_media/resources/fpga/peripherals/spi-engine3.pdf>`.
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* :ref:`spi_engine tutorial`.
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