zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/common/c5soc/system_project.tcl

11 lines
257 B
Tcl
Raw Normal View History

projects/common: Add build files templates carriers. Modified Quartus Versions The build files are available for the following carriers: * intel: a10gx, a10soc, c5soc, de10nano, s10soc * xilinx: coraz7s, kc705, kcu105, vc707, vc709, vck190, vcu118, vcu128, vmk180, zc702, zc706, zcu102, zed * Added Makefiles, system_constr.sdc, system_qsys intel * Added Makefiles, system_bd, system_constr xilinx * de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0 according to last commit update Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-26 19:12:04 +00:00
set REQUIRED_QUARTUS_VERSION 21.1.0
projects/common: Add system_top _project templates Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct code and modify according to guidelines * Added spacing to ports declaration * Corrected coding mistakes/misspelling * Modified/added variables names * Added seetings (intel) and removed specific optimization settings * Added assignments to unassigned pins (gpios) Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct/Add missing wrapper ports and iobufs * Added port in wrapper (mainly spi) according to base design file * Added instances of iobufs where missing * Corrected gpio assignments or added missing ones * Corrected minor guidelines mistakes Signed-off-by: laurent-19 <laurentiu.popa@analog.com> ac701/system_top.v: Change top based on previous projects * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> projects/common: Modify templates to build without errors * Changed path for adi_env.tcl * Moved adi_project command before assign intel * Removed unnecessary spi signals * Added spi ports with default logic * a10soc: Removed pl-ddr signals and ports * ac701: system_bd: Modified mdio interface system_project: Added adi_board, adiobuf sourcing system_top: Removed hdmi, i2c, fanpwm, spdif ports according to base design * c5soc: Added version settings Removed unused gpios * microzed: system_bd: Enabled RTS1 to use FCLK system_top: Removed hdmi, i2c, unused gpios * vc709: Separated input from ouput gpio, according to bd Removed unnecessary ports Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Delete microzed vmk_es templates * Removed hp0 interconnect from cora base design * Added extra line to files de10nano Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-06-23 14:52:51 +00:00
set QUARTUS_PRO_ISUSED 0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_project_intel.tcl
adi_project template_c5soc
source $ad_hdl_dir/projects/common/c5soc/c5soc_system_assign.tcl
execute_flow -compile