314 lines
12 KiB
ReStructuredText
314 lines
12 KiB
ReStructuredText
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.. _axi_ad9783:
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AXI AD9783
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI AD9783 <library/axi_ad9783>` IP core
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can be used to interface the :adi:`AD9783` device.
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It is a dual DAC with 16 bits resolution, interfaced through LVDS, and with sample
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rates up to 500 MSPS. This documentation only covers the IP core and requires
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that one must be familiar with the device for a complete and better understanding.
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More about the generic framework interfacing DACs can be read in :ref:`axi_dac`.
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Features
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--------------------------------------------------------------------------------
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* AXI Memory-Mapped to Streaming control/status interface
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* PRBS monitoring
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* Internal DDS
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* BIST testing
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* Supports only Xilinx devices
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_ad9783/axi_ad9783.v`
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- Verilog source for the AXI AD9783.
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* - :git-hdl:`library/common/up_dac_common.v`
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- Verilog source for the DAC Common regmap.
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* - :git-hdl:`library/common/up_dac_channel.v`
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- Verilog source for the DAC Channel regmap.
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Functional Description
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--------------------------------------------------------------------------------
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The axi_ad9783 cores architecture contains:
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* :git-hdl:`Interface <library/axi_ad9783/axi_ad9783.v#L135>`
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module in LVDS mode for Xilinx devices
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* :git-hdl:`Transmit <library/axi_ad9783/axi_ad9783_core.v>`
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module, which contains:
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* :git-hdl:`DAC channel processing <axi_ad9783/axi_ad9783_channel.v>` modules, one for each channel
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* Different data generators (:git-hdl:`DDS <library/common/ad_dds.v>`, pattern, PRBS)
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* :git-hdl:`DAC Channel register map <library/common/up_dac_channel.v>`
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* :git-hdl:`DAC Common register map <library/common/up_dac_common.v>`
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* :git-hdl:`AXI control and status <library/common/up_axi.v>` modules.
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Device Interface Description
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The interface also provides a single clock tree for the entire core. This clock
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uses a global buffer that has the minimum skew all across the die. On Xilinx
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devices, this is done via the IBUFGDS, BUFGCE_DIV and BUFG primitives. The clock
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``dac_clk_in_p`` is passed through these primitives in order to obtain the
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divided clock: through IBUFGDS, then BUFGCE_DIV to BUFG. The core and the
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interface run at the same clock frequency.
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Internal Interface Description
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The main purpose of all (including this) ADI IP cores is to provide a common,
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well-defined internal interface within the FPGA. This interface consists of the
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following signals per channel, except for VALID which is common to all channels.
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VALID
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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It is always set to logic 1 and indicates a valid sample on each DATA port.
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Because it is in the transmit (DAC) direction, this indicates the current sample
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is being read by the core.
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ENABLE
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The enable signal is only for software use and it is controlled by the
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corresponding register bit. The core simply reflects the programmed bit as an
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output port. In ADI reference projects, this bit is used to activate the channel
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that one is interested in. It is then used by the UPACK core to route the data
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based on total number of channels and the selected number of channels. As an
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example, AXI_AD9783 supports a total of 2 channels, 64 bits each. Because the
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SERDES factor was chosen to be 8, we have 4 samples of 16 bits each, on I
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channel and Q channel also, resulting in DMA with 128 bits as data width.
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DATA
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The DATA is the raw analog samples, and 4096 samples generated by PRBS are sent.
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It follows two simple rules.
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#. The samples are always 16 bits. In the transmit direction, if the DAC data
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width is less than 16 bits, the most significant bits are used. This allows
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the same destination portable across different DAC data widths. In other
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words, if the source is generating a 16 bits tone, the signal appears the
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same across a 12 bit, 14 bit or 16 bit DAC with only the corresponding
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amplitude change. The source can thus be independent of the number of bits
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supported by DAC.
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#. The DATA is received and transmitted with most significant sample "newest"
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regardless of the channel width. In other words, the most significant sample
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is the "newest" sample. If the total channel width is 64 bits, it carries 4
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samples (16 bits) per clock. If we were to name these samples as S3 (bits 63
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down to 48), S2 (bits 47 down to 32), S1 (bits 31 down to 16) and S0 (bits 15
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down to 0), the following is true. In the transmit direction, S0 is sent
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first and S3 is sent last to the DAC. The analog samples are S0, S1, S2 and
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S3 across time with S0 being the oldest and S3 being the newest sample.
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Parallel data port interface
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-------------------------------------------------------------------------------
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The parallel port data interface consists of up to 18 differential signals,
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``dac_clk_out_*``, ``dac_clk_in_*``, and up to 16 data lines
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(``dac_data_out_*``\ [15:0]).
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DCO is the output clock generated by the AD9783 that is used to clock out the
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data from the digital data engine.
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The data lines transmit the multiplexed I and Q data words for the I and Q
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DACs, respectively.
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DCI provides timing information about the parallel data and signals the I/Q
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status of the data.
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The incoming LVDS data is latched by an internally generated clock referred to
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as the data sampling signal (DSS). DSS is a delayed version of the main DAC
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clock signal.
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The clock input signal provides timing information about the parallel data, as
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well as indicating the destination (that is, I DAC or Q DAC) of the data. The
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data that is processed on rising edge will be outputted on the I DAC, and the
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data that is on falling edge will be outputted on Q DAC (see figure below).
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.. image:: parallel_interface.svg
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:alt: AXI AD9783 parallel interface
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Calibration of the device
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-------------------------------------------------------------------------------
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Calibrating the device means finding the proper value for the SMP_DLY register
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(see datasheet) in order for the PRBS function (PN23 in this case) to work
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properly when generating the 4096 samples of data.
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The BIST feature in the AD9783 is a simple type adder and is a user
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synchronizable BIST feature. When a reading is performed, it adds up all the
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data that was generated on the rising edges of the ``dac_div_clk`` and it
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writes it in the registers accessible by the user: the low part of the result
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is written in register 0x1B, and the high part in 0x1C. For the sum of data
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from falling edges, read 0x1D and 0x1E respectively.
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.. code::
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register 0x1A <- 0x20
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register 0x1A <- 0x00 # to clear the BIST registers
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register 0x1A <- 0x80 # enable BIST
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# 4096 samples generated by PN23 are sent
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# send zeroes
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register 0x1A <- 0xC0 # perform BIST read
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# read registers 0x1B, 0x1C for the sum of data from rising edges
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# read registers 0x1D, 0x1E for the sum of data from falling edges
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In register 0x1A, write 0x20 then 0x00 to clear the BIST registers while the
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IP is writing zeros to the data bits. To enable BIST, write 0x80 to register
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0x1A. Afterwards, 4096 samples of data are generated by PN23 PRBS and are sent
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to the data inputs.
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When all samples are sent, the IP is continuously sending zeros after the
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samples, while the BIST read is being performed. Sending zeroes after the
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samples is required in order to maintain the sums unchanged in the registers.
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Perform a BIST read by writing 0xC0 to register 0x1A to receive the unique sum
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of rising edge data in register 0x1B and register 0x1C and a unique sum of
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falling edge data in register 0x1D and register 0x1E. These register contents
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must always give the same values for the same samples each time they are sent.
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In order to change what data is sent, the DAC_DDS_SEL register value should be
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changed. To send PN23, 0x9 should be written in the register. The address for
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the DAC_DDS_SEL register is calculated by adding 0x418 (for the first channel)
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to the offset found in the devicetree, for the device.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:width: 600
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:alt: AXI AD9783 block diagram
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - ID
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- Core ID should be unique for each IP in the system
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* - FPGA_TECHNOLOGY
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- Encoded value describing the technology/generation of the FPGA device
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* - FPGA_FAMILY
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- Encoded value describing the family variant of the FPGA device
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* - SPEED_GRADE
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- Encoded value describing the FPGA's speed-grade
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* - DEV_PACKAGE
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- Encoded value describing the device package. The package might affect
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high-speed interfaces
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* - DAC_DDS_TYPE
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- 1 for CORDIC or 2 for Polynomial
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* - DAC_DDS_CORDIC_DW
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- CORDIC DDS data width
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* - DAC_DDS_CORDIC_PHASE_DW
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- CORDIC DDS phase width
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* - DAC_DATAPATH_DISABLE
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- Disable DAC processing blocks. Disables DDS
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.. note::
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Make sure these parameters have the appropriate values set.
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - dac_clk_in_p
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- LVDS input clock; comes from DCOP/N of the AD9783 chip
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* - dac_clk_in_n
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- LVDS input clock; comes from DCOP/N of the AD9783 chip
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* - dac_clk_out_p
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- LVDS output clock; goes to DCIP/N of the AD9783 chip
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* - dac_clk_out_n
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- LVDS output clock; goes to DCIP/N of the AD9783 chip
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* - dac_data_out_p
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- LVDS output data lines
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* - dac_data_out_n
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- LVDS output data lines
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* - dac_div_clk
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- Frequency divided clock used for clocking the DMA and the UPACK; it is
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1/4 compared to the reference input clock
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* - dac_rst
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- Core reset signal
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* - dac_enable_*
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- If set, the channel is enabled (one for each channel)
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* - dac_valid
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- Indicates valid data request for all channels
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* - dac_ddata_*
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- Transmitted data output (one for each channel)
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* - dac_dunf
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- Data underflow, must be connected to the DMA
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* - s_axi
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- Standard AXI Slave Memory Map interface
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Register Map
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--------------------------------------------------------------------------------
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The register map of the core contains instances of several generic register maps
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like ADC common, ADC channel, DAC common, DAC channel etc. The following table
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presents the base addresses of each instance, after that can be found the
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detailed description of each generic register map. The absolute address of a
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register should be calculated by adding the instance base address to the
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registers relative address.
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.. list-table:: Register Map base addresses for axi_ad9783
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:header-rows: 1
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* - DWORD
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- BYTE
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- Name
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- Description
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* - 0x0000
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- 0x0000
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- BASE
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- See the `Base <#hdl-regmap-COMMON>`__ table for more details.
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* - 0x1000
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- 0x4000
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- TX COMMON
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- See the `DAC Common <#hdl-regmap-DAC_COMMON>`__ table for more details.
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* - 0x1000
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- 0x4000
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- TX CHANNELS
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- See the `DAC Channel <#hdl-regmap-DAC_CHANNEL>`__ table for more details.
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.. hdl-regmap::
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:name: COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: DAC_COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: DAC_CHANNEL
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:no-type-info:
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Software Guidelines
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--------------------------------------------------------------------------------
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The software for this IP can be found as part of the ZCU102 Reference Design
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at :git-linux:`/`.
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The IP expects the software run a calibration at least once. It has to find
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out what value for the SMP_DLY (see in datasheet) is good for the PRBS to
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work.
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References
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-------------------------------------------------------------------------------
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* :git-hdl:`library/axi_ad9783`
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* :adi:`AD9783`
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* :git-linux:`/`
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* :adi:`EVAL-AD9783 <en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9783.html>`
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* :dokuwiki:`EVAL-AD9783 with ZCU102 reference design description <resources/fpga/xilinx/interposer/ad9783>`
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* :xilinx:`Ultrascale SelectIO <support/documentation/user_guides/ug571-ultrascale-selectio.pdf>`
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* :xilinx:`UltraScale Architecture Clocking Resources User Guide <support/documentation/user_guides/ug572-ultrascale-clocking.pdf>`
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