2023-08-16 12:57:14 +00:00
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.. _spi_engine spi-bus-interface:
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SPI Bus Interface
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================================================================================
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The SPI bus interface carries logical low-level SPI bus signals.
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Files
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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2024-02-28 13:31:46 +00:00
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* - :git-hdl:`library/spi_engine/interfaces/spi_engine_rtl.xml`
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2023-08-16 12:57:14 +00:00
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- Interface definition file
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Signal Pins
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.. list-table::
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:widths: 10 15 65
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:header-rows: 1
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* - Name
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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- Direction (Controller)
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2023-08-16 12:57:14 +00:00
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- Description
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* - ``sclk``
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- Output
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- SPI Clock.
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* - ``sdo``
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- Output
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- SPI SDO (MOSI) signal.
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* - ``sdo_t``
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- Output
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- ``sdo`` tri-state enable. If 1 the MOSI signal should be tristated and
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not be connected to ``sdo``
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* - ``sdi``
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- Input
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- SPI SDI (MISO) signal. Execution module supports max 8 individual
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``sdi`` lines.
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* - ``cs``
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- Output
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- SPI chip-select signal.
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* - ``three_wire``
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- Output
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- If set to 1 the bus should operate in three-wire mode. In three-wire
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mode ``sdi`` is connected to MOSI instead of MISO.
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IO configuration
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.. image:: spi_bus.svg
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:width: 30%
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:align: right
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The SPI bus interface only carries a logical representation of the low-level SPI
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bus signals. The top-level module in the FPGA design project is responsible for
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translating the signal to physical SPI bus signals by instantiating and
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connecting it to appropriate IO primitives.
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The ``sclk`` and ``cs`` signals can typically be directly connected to a output
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buffer. ``sdi`` should be connected to a mux, that depending on the setting of
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the ``three_wire`` signal connects to a input buffer connected to the ``miso``
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signal or to a input buffer connected to the ``mosi`` signal. The ``sdo`` signal
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should be connected to a output tri-state buffer with the ``sdo_t`` signal
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controlling the tri-state setting.
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In some configurations three-wire support may not be required and ``sdi`` can
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directly be connected to the input buffer for the ``miso`` signal. Similarly
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when ``mosi`` tri-stating is not required the ``sdo`` signal can be directly
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connected to the ``mosi`` signal leaving the ``sdo_t`` signal unconnected.
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2023-08-18 20:29:31 +00:00
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Example Verilog IO configuration
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The following example Verilog code shows the most generic IO configuration,
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which represents the diagram above. Depending on system requirements some
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simplification might be possible.
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Signals with phy prefix are assumed to be connected to the physical input/output
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pins and signals with the spi prefix are assumed to be connected SPI-Engine bus
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interface.
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.. code-block:: verilog
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assign phy_sclk = spi_sclk;
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assign phy_cs = spi_cs;
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assign phy_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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assign spi_sdi = spi_three_wire ? phy_mosi : phy_miso;
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