2022-09-21 12:12:35 +00:00
TITLE
Base (common to all cores)
2023-08-07 19:31:41 +00:00
COMMON
2022-09-21 12:12:35 +00:00
ENDTITLE
############################################################################################
############################################################################################
REG
0x0000
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
VERSION
2022-09-21 12:12:35 +00:00
Version and Scratch Registers
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
VERSION
2022-09-21 12:12:35 +00:00
RO
Version number. Unique to all cores.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0001
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
ID
2022-09-21 12:12:35 +00:00
Version and Scratch Registers
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
ID
2022-09-21 12:12:35 +00:00
RO
Instance identifier number.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0002
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
SCRATCH
2022-09-21 12:12:35 +00:00
Version and Scratch Registers
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
SCRATCH
2022-09-21 12:12:35 +00:00
RW
Scratch register.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0003
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
CONFIG
2022-09-21 12:12:35 +00:00
Version and Scratch Registers
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
2022-09-21 12:12:35 +00:00
IQCORRECTION_DISABLE
RO
If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
2022-09-21 12:12:35 +00:00
DCFILTER_DISABLE
RO
If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[2] 0x00000000
2022-09-21 12:12:35 +00:00
DATAFORMAT_DISABLE
RO
If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[3] 0x00000000
2022-09-21 12:12:35 +00:00
USERPORTS_DISABLE
RO
If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[4] 0x00000000
2022-09-21 12:12:35 +00:00
MODE_1R1T
RO
If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[5] 0x00000000
2022-09-21 12:12:35 +00:00
DELAY_CONTROL_DISABLE
RO
If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[6] 0x00000000
2022-09-21 12:12:35 +00:00
DDS_DISABLE
RO
If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7] 0x00000000
2022-09-21 12:12:35 +00:00
CMOS_OR_LVDS_N
RO
CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[8] 0x00000000
2022-09-21 12:12:35 +00:00
PPS_RECEIVER_ENABLE
RO
If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[9] 0x00000000
2022-09-21 12:12:35 +00:00
SCALECORRECTION_ONLY
RO
If set, indicates that the IQ Correction module implements only scale correction.
IQ correction must be enabled. (as a result of a configuration of the IP instance)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[12] 0x00000000
2022-09-21 12:12:35 +00:00
EXT_SYNC
RO
If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
ENDFIELD
2022-10-06 11:37:43 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[13] 0x00000000
2022-10-06 11:37:43 +00:00
RD_RAW_DATA
2023-03-07 15:34:51 +00:00
RO
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.
2022-10-06 11:37:43 +00:00
ENDFIELD
2022-09-21 12:12:35 +00:00
############################################################################################
############################################################################################
REG
0x0004
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
PPS_IRQ_MASK
2022-09-21 12:12:35 +00:00
PPS Interrupt mask
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000001
2022-09-21 12:12:35 +00:00
PPS_IRQ_MASK
RW
Mask bit for the 1PPS receiver interrupt
ENDFIELD
############################################################################################
############################################################################################
REG
0x0007
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
FPGA_INFO
2023-08-07 19:31:41 +00:00
FPGA device information
docs: links, drop part, fixups, codeowners
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
:git-hdl:`library/scripts/adi_intel_device_info_enc.tcl` (Intel encoded values)
:git-hdl:`library/scripts/adi_xilinx_device_info_enc.tcl` (Xilinx encoded values)
2022-09-21 12:12:35 +00:00
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:24] 0x00000000
2022-09-21 12:12:35 +00:00
FPGA_TECHNOLOGY
RO
Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[23:16] 0x00000000
2022-09-21 12:12:35 +00:00
FPGA_FAMILY
RO
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:8] 0x00000000
2022-09-21 12:12:35 +00:00
SPEED_GRADE
RO
Encoded value describing the FPGA's speed-grade
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000000
2022-09-21 12:12:35 +00:00
DEV_PACKAGE
RO
Encoded value describing the device package. The package might affect high-speed interfaces
ENDFIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
2022-09-21 12:12:35 +00:00
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