pluto_hdl_adi/library/axi_ad3552r/axi_ad3552r_if_tb

#!/bin/bash

SOURCE="$0.v"
SOURCE+=" axi_ad3552r_if.v"

cd `dirname $0`
source ../common/tb/run_tb.sh
library/axi_ad3552r: Added interface IP for Xilinx projects. The custom interface IP for AD3552R DAC has more operation capabilities: - 8b register read/write SDR/DDR - 16b register read/write SDR/DDR - data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) - selectable input source : DMA/ADC/TEST_RAMP - data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode - the IP reference clock (clk_in) can have a maximum frequency of 132MHz - the IP has multiple device synchronization capability when the DMA is set as an input data source Signed-off-by: PopPaul2021 <Paul.Pop@analog.com> 2023-09-07 06:14:35 +00:00			`#!/bin/bash`

			`SOURCE="$0.v"`
			`SOURCE+=" axi_ad3552r_if.v"`

			cd `dirname $0`
			`source ../common/tb/run_tb.sh`