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pluto_hdl_adi/library/axi_pwm_gen/Makefile

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axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
####################################################################################
axi_pwm_gen: New features and fixes New features: 1. External sync force the phase align. The external sync was used to align the phases of enabled pwms, but only after being armed by a load_config signal toggle. This feature lets the user decide between using load_config to arm and wait for a neg-edge of sync or automatic phase align trigger on the ext_sync neg-edge. 2. Force align. Lets the user chose between immediately stopping the active pulses and realigning them, or waiting for all running pulse periods end, before realigning. 3. Start at sync. When this feature is activated, the pulses will start immediately after the trigger event. Otherwise, each pulse will start after a period equal to the one for which it is set. 4. Use parameters to set the default status after reset of the - soft reset - start at sync - force align - ext sync align Update regmap. Fixes: 1. The polarity on disabled channels was staying high instead of low. 2. Fix 0 and 100 proc duty cycle configuration. Signed-off-by: AndreiGrozav <andrei.grozav@analog.com> Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
2024-03-22 17:09:27 +00:00
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
### SPDX short identifier: BSD-1-Clause
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_pwm_gen
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
axi_pwm_gen: Add support for 16 channels Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com> Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-11-07 08:45:14 +00:00
GENERIC_DEPS += axi_pwm_gen.sv
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
GENERIC_DEPS += axi_pwm_gen_1.v
axi_pwm_gen: Add support for 16 channels Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com> Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-11-07 08:45:14 +00:00
GENERIC_DEPS += axi_pwm_gen_regmap.sv
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_pwm_gen_constr.ttcl
XILINX_DEPS += axi_pwm_gen_ip.tcl
XILINX_LIB_DEPS += util_cdc
axi_pwm_gen: add: intel support (#1080) Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
2023-02-07 10:27:04 +00:00
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
axi_pwm_gen: Update timing constraints, hw.tcl and sdc files. Not using util_cdc_constr.tcl
2023-02-20 10:27:57 +00:00
INTEL_DEPS += ../util_cdc/sync_bits.v
INTEL_DEPS += ../util_cdc/sync_data.v
axi_pwm_gen: New features and fixes New features: 1. External sync force the phase align. The external sync was used to align the phases of enabled pwms, but only after being armed by a load_config signal toggle. This feature lets the user decide between using load_config to arm and wait for a neg-edge of sync or automatic phase align trigger on the ext_sync neg-edge. 2. Force align. Lets the user chose between immediately stopping the active pulses and realigning them, or waiting for all running pulse periods end, before realigning. 3. Start at sync. When this feature is activated, the pulses will start immediately after the trigger event. Otherwise, each pulse will start after a period equal to the one for which it is set. 4. Use parameters to set the default status after reset of the - soft reset - start at sync - force align - ext sync align Update regmap. Fixes: 1. The polarity on disabled channels was staying high instead of low. 2. Fix 0 and 100 proc duty cycle configuration. Signed-off-by: AndreiGrozav <andrei.grozav@analog.com> Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
2024-03-22 17:09:27 +00:00
INTEL_DEPS += ../util_cdc/sync_event.v
axi_pwm_gen: Update timing constraints, hw.tcl and sdc files. Not using util_cdc_constr.tcl
2023-02-20 10:27:57 +00:00
INTEL_DEPS += axi_pwm_gen_constr.sdc
axi_pwm_gen: add: intel support (#1080) Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
2023-02-07 10:27:04 +00:00
INTEL_DEPS += axi_pwm_gen_hw.tcl
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
include ../scripts/library.mk