zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/jesd204/jesd204_common/jesd204_common_ip.tcl

32 lines
1.0 KiB
Tcl
Raw Normal View History

Add copyright & license for all files needing ADI JESD specific license * Added every year when the file was edited, with comma * Range if it's consecutive years Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-18 07:55:04 +00:00
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
adi_ip_create jesd204_common
jesd204-sub-ip- no top files
2017-06-01 19:48:48 +00:00
add_files -fileset [get_filesets sources_1] [list \
jesd204: Fix file names All the file names must have the same name as its module. Change all the files, which did not respect this rule. Update all the make files and Tcl scripts.
2018-03-28 13:44:06 +00:00
"jesd204_lmfc.v" \
"jesd204_scrambler.v" \
jesd204_common: Added JESD204C components
2019-10-02 13:25:40 +00:00
"jesd204_scrambler_64b.v" \
"jesd204_crc12.v" \
jesd204: Fix file names All the file names must have the same name as its module. Change all the files, which did not respect this rule. Update all the make files and Tcl scripts.
2018-03-28 13:44:06 +00:00
"jesd204_eof_generator.v" \
jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode, and frame alignment character replace/insert with or without scrambling. Add support for xcelium simulator to jesd204/tb Increased cores minor version.
2020-01-30 22:05:13 +00:00
"jesd204_frame_mark.v" \
"jesd204_frame_align_replace.v" \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
"pipeline_stage.v" \
]
Fix error regarding hierarchy that Vivado misses * Solution from here: https://support.xilinx.com/s/article/69320?language=en_US * Added in: * util_cdc * util_cic * jesd204_rx/tx * util_upack2 * axi_jesd204_common: used in axi_jesd204_rx/tx * axi_jesd204_rx/tx * jesd_common Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-06-27 12:57:14 +00:00
set_property source_mgmt_mode DisplayOnly [current_project]
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
adi_ip_properties_lite jesd204_common
jesd204_common: Added JESD204C components
2019-10-02 13:25:40 +00:00
set_property display_name "ADI JESD204C Common Library" [ipx::current_core]
set_property description "ADI JESD204C Common Library" [ipx::current_core]
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
set_property hide_in_gui {1} [ipx::current_core]
library: jesd204: Fixup Vivado exiting with error (#1243) The lack of the create_xgui_files causes Vivado to exit with an error when running multiple Vivado instances (parallel make case) Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-01-16 12:43:03 +00:00
ipx::create_xgui_files [ipx::current_core]
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ipx::save_core [ipx::current_core]