zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/ad3552r_evb/zed/system_project.tcl

18 lines
660 B
Tcl
Raw Normal View History

projects/ad3552r_evb: Added project for AD3552R-EVB on ZedBoard. The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC. The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal. If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS. If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS. The VADJ voltage should be set to 1.8V. Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
2023-09-07 06:20:25 +00:00
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad3552r_evb_zed
adi_project_files ad3552r_evb_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" ]
adi_project_run ad3552r_evb_zed