2023-07-10 08:38:46 +00:00
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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2023-10-18 07:28:11 +00:00
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N
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2021-01-21 10:05:11 +00:00
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# input delays for MISO lines (SDO for the device)
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# data is latched on negative edge
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set tsetup 5.6
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set thold 1.4
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}]
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