2023-07-10 08:38:46 +00:00
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###############################################################################
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## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2021-11-02 10:05:42 +00:00
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# constraints
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set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports sys_rst]
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# clocks
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p]
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set_property -dict {PACKAGE_PIN G18 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n]
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# uart
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set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports uart_sin]
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set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports uart_sout]
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# fan
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set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
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set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
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set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
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set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
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set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
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set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
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set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
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set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
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set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
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set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_N
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set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_E
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set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_S
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set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
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set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
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set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0_LS
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set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1_LS
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set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2_LS
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set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3_LS
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set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4_LS
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set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5_LS
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set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6_LS
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set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7_LS
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# iic
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set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
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set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
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#Setting the Configuration Bank Voltage Select
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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# Create SPI clock
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create_generated_clock -name spi_clk \
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-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]
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