2023-07-10 08:36:06 +00:00
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###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2018-03-20 13:43:36 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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# Maximum lane rate of 14.2 Gbps however the dacfifo does not meet the 355 MHz requirement, reducing it to 333MHz
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create_clock -period "3 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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# Asynchronous GPIOs
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foreach async_input {gpio_bd_i[*]} {
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set_false_path -from [get_ports $async_input]
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}
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foreach async_output {gpio_bd_o[*] txen_0 txen_1 spi_en_n} {
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set_false_path -to [get_ports $async_output]
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}
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derive_pll_clocks
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derive_clock_uncertainty
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